NHS31xx SW API
core_cm0plus.h
1 /**************************************************************************/
23 #if defined ( __ICCARM__ )
24  #pragma system_include /* treat file as system include file for MISRA check */
25 #endif
26 
27 #ifdef __cplusplus
28  extern "C" {
29 #endif
30 
31 #ifndef __CORE_CM0PLUS_H_GENERIC
32 #define __CORE_CM0PLUS_H_GENERIC
33 
48 /*******************************************************************************
49  * CMSIS definitions
50  ******************************************************************************/
56 /* CMSIS CM0P definitions */
57 #define __CM0PLUS_CMSIS_VERSION_MAIN (0x03)
58 #define __CM0PLUS_CMSIS_VERSION_SUB (0x01)
59 #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
60  __CM0PLUS_CMSIS_VERSION_SUB)
62 #define __CORTEX_M (0x00)
65 #if defined ( __CC_ARM )
66  #define __ASM __asm
67  #define __INLINE __inline
68  #define __STATIC_INLINE static __inline
69 
70 #elif defined ( __ICCARM__ )
71  #define __ASM __asm
72  #define __INLINE inline
73  #define __STATIC_INLINE static inline
74 
75 #elif defined ( __GNUC__ )
76  #define __ASM __asm
77  #define __INLINE inline
78  #define __STATIC_INLINE static inline
80 #elif defined ( __TASKING__ )
81  #define __ASM __asm
82  #define __INLINE inline
83  #define __STATIC_INLINE static inline
84 
85 #endif
86 
89 #define __FPU_USED 0
90 
91 #if defined ( __CC_ARM )
92  #if defined __TARGET_FPU_VFP
93  #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
94  #endif
95 
96 #elif defined ( __ICCARM__ )
97  #if defined __ARMVFP__
98  #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
99  #endif
100 
101 #elif defined ( __GNUC__ )
102  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
103  #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
104  #endif
105 
106 #elif defined ( __TASKING__ )
107  #if defined __FPU_VFP__
108  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
109  #endif
110 #endif
111 
112 #include <stdint.h> /* standard types definitions */
113 #include <core_cmInstr.h> /* Core Instruction Access */
114 #include <core_cmFunc.h> /* Core Function Access */
115 
116 #endif /* __CORE_CM0PLUS_H_GENERIC */
117 
119 #ifndef __CMSIS_GENERIC
120 
121 #ifndef __CORE_CM0PLUS_H_DEPENDANT
122 #define __CORE_CM0PLUS_H_DEPENDANT
123 
124 /* check device defines and use defaults */
125 #if defined __CHECK_DEVICE_DEFINES
126  #ifndef __CM0PLUS_REV
127  #define __CM0PLUS_REV 0x0000
128  #warning "__CM0PLUS_REV not defined in device header file; using default!"
129  #endif
130 
131  #ifndef __MPU_PRESENT
132  #define __MPU_PRESENT 0
133  #warning "__MPU_PRESENT not defined in device header file; using default!"
134  #endif
135 
136  #ifndef __VTOR_PRESENT
137  #define __VTOR_PRESENT 0
138  #warning "__VTOR_PRESENT not defined in device header file; using default!"
139  #endif
140 
141  #ifndef __NVIC_PRIO_BITS
142  #define __NVIC_PRIO_BITS 2
143  #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
144  #endif
145 
146  #ifndef __Vendor_SysTickConfig
147  #define __Vendor_SysTickConfig 0
148  #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
149  #endif
150 #endif
151 
152 /* IO definitions (access restrictions to peripheral registers) */
161 #ifdef __cplusplus
162  #define __I volatile
163 #else
164  #define __I volatile const
165 #endif
166 #define __O volatile
167 #define __IO volatile
172 /*******************************************************************************
173  * Register Abstraction
174  Core Register contain:
175  - Core Register
176  - Core NVIC Register
177  - Core SCB Register
178  - Core SysTick Register
179  - Core MPU Register
180  ******************************************************************************/
181 
194 typedef union
195 {
196  struct
197  {
198 #if (__CORTEX_M != 0x04)
199  uint32_t _reserved0:27;
200 #else
201  uint32_t _reserved0:16;
202  uint32_t GE:4;
203  uint32_t _reserved1:7;
204 #endif
205  uint32_t Q:1;
206  uint32_t V:1;
207  uint32_t C:1;
208  uint32_t Z:1;
209  uint32_t N:1;
210  } b;
211  uint32_t w;
212 } APSR_Type;
213 
214 
217 typedef union
218 {
219  struct
220  {
221  uint32_t ISR:9;
222  uint32_t _reserved0:23;
223  } b;
224  uint32_t w;
225 } IPSR_Type;
226 
227 
230 typedef union
231 {
232  struct
233  {
234  uint32_t ISR:9;
235 #if (__CORTEX_M != 0x04)
236  uint32_t _reserved0:15;
237 #else
238  uint32_t _reserved0:7;
239  uint32_t GE:4;
240  uint32_t _reserved1:4;
241 #endif
242  uint32_t T:1;
243  uint32_t IT:2;
244  uint32_t Q:1;
245  uint32_t V:1;
246  uint32_t C:1;
247  uint32_t Z:1;
248  uint32_t N:1;
249  } b;
250  uint32_t w;
251 } xPSR_Type;
252 
253 
256 typedef union
257 {
258  struct
259  {
260  uint32_t nPRIV:1;
261  uint32_t SPSEL:1;
262  uint32_t FPCA:1;
263  uint32_t _reserved0:29;
264  } b;
265  uint32_t w;
266 } CONTROL_Type;
267 
279 typedef struct
280 {
281  __IO uint32_t ISER[1];
282  uint32_t RESERVED0[31];
283  __IO uint32_t ICER[1];
284  uint32_t RSERVED1[31];
285  __IO uint32_t ISPR[1];
286  uint32_t RESERVED2[31];
287  __IO uint32_t ICPR[1];
288  uint32_t RESERVED3[31];
289  uint32_t RESERVED4[64];
290  __IO uint32_t IP[8];
291 } NVIC_Type;
292 
304 typedef struct
305 {
306  __I uint32_t CPUID;
307  __IO uint32_t ICSR;
308 #if (__VTOR_PRESENT == 1)
309  __IO uint32_t VTOR;
310 #else
311  uint32_t RESERVED0;
312 #endif
313  __IO uint32_t AIRCR;
314  __IO uint32_t SCR;
315  __IO uint32_t CCR;
316  uint32_t RESERVED1;
317  __IO uint32_t SHP[2];
318  __IO uint32_t SHCSR;
319 } SCB_Type;
320 
321 /* SCB CPUID Register Definitions */
322 #define SCB_CPUID_IMPLEMENTER_Pos 24
323 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
325 #define SCB_CPUID_VARIANT_Pos 20
326 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)
328 #define SCB_CPUID_ARCHITECTURE_Pos 16
329 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
331 #define SCB_CPUID_PARTNO_Pos 4
332 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)
334 #define SCB_CPUID_REVISION_Pos 0
335 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos)
337 /* SCB Interrupt Control State Register Definitions */
338 #define SCB_ICSR_NMIPENDSET_Pos 31
339 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos)
341 #define SCB_ICSR_PENDSVSET_Pos 28
342 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)
344 #define SCB_ICSR_PENDSVCLR_Pos 27
345 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)
347 #define SCB_ICSR_PENDSTSET_Pos 26
348 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)
350 #define SCB_ICSR_PENDSTCLR_Pos 25
351 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)
353 #define SCB_ICSR_ISRPREEMPT_Pos 23
354 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)
356 #define SCB_ICSR_ISRPENDING_Pos 22
357 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)
359 #define SCB_ICSR_VECTPENDING_Pos 12
360 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
362 #define SCB_ICSR_VECTACTIVE_Pos 0
363 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)
365 #if (__VTOR_PRESENT == 1)
366 /* SCB Interrupt Control State Register Definitions */
367 #define SCB_VTOR_TBLOFF_Pos 7
368 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
369 #endif
370 
371 /* SCB Application Interrupt and Reset Control Register Definitions */
372 #define SCB_AIRCR_VECTKEY_Pos 16
373 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
375 #define SCB_AIRCR_VECTKEYSTAT_Pos 16
376 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
378 #define SCB_AIRCR_ENDIANESS_Pos 15
379 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)
381 #define SCB_AIRCR_SYSRESETREQ_Pos 2
382 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
384 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1
385 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
387 /* SCB System Control Register Definitions */
388 #define SCB_SCR_SEVONPEND_Pos 4
389 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)
391 #define SCB_SCR_SLEEPDEEP_Pos 2
392 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)
394 #define SCB_SCR_SLEEPONEXIT_Pos 1
395 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)
397 /* SCB Configuration Control Register Definitions */
398 #define SCB_CCR_STKALIGN_Pos 9
399 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)
401 #define SCB_CCR_UNALIGN_TRP_Pos 3
402 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)
404 /* SCB System Handler Control and State Register Definitions */
405 #define SCB_SHCSR_SVCALLPENDED_Pos 15
406 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
419 typedef struct
420 {
421  __IO uint32_t CTRL;
422  __IO uint32_t LOAD;
423  __IO uint32_t VAL;
424  __I uint32_t CALIB;
425 } SysTick_Type;
426 
427 /* SysTick Control / Status Register Definitions */
428 #define SysTick_CTRL_COUNTFLAG_Pos 16
429 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos)
431 #define SysTick_CTRL_CLKSOURCE_Pos 2
432 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)
434 #define SysTick_CTRL_TICKINT_Pos 1
435 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos)
437 #define SysTick_CTRL_ENABLE_Pos 0
438 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos)
440 /* SysTick Reload Register Definitions */
441 #define SysTick_LOAD_RELOAD_Pos 0
442 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)
444 /* SysTick Current Register Definitions */
445 #define SysTick_VAL_CURRENT_Pos 0
446 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)
448 /* SysTick Calibration Register Definitions */
449 #define SysTick_CALIB_NOREF_Pos 31
450 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos)
452 #define SysTick_CALIB_SKEW_Pos 30
453 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos)
455 #define SysTick_CALIB_TENMS_Pos 0
456 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)
460 #if (__MPU_PRESENT == 1)
461 
469 typedef struct
470 {
471  __I uint32_t TYPE;
472  __IO uint32_t CTRL;
473  __IO uint32_t RNR;
474  __IO uint32_t RBAR;
475  __IO uint32_t RASR;
476 } MPU_Type;
477 
478 /* MPU Type Register */
479 #define MPU_TYPE_IREGION_Pos 16
480 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos)
482 #define MPU_TYPE_DREGION_Pos 8
483 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos)
485 #define MPU_TYPE_SEPARATE_Pos 0
486 #define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos)
488 /* MPU Control Register */
489 #define MPU_CTRL_PRIVDEFENA_Pos 2
490 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos)
492 #define MPU_CTRL_HFNMIENA_Pos 1
493 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos)
495 #define MPU_CTRL_ENABLE_Pos 0
496 #define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos)
498 /* MPU Region Number Register */
499 #define MPU_RNR_REGION_Pos 0
500 #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos)
502 /* MPU Region Base Address Register */
503 #define MPU_RBAR_ADDR_Pos 8
504 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)
506 #define MPU_RBAR_VALID_Pos 4
507 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos)
509 #define MPU_RBAR_REGION_Pos 0
510 #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos)
512 /* MPU Region Attribute and Size Register */
513 #define MPU_RASR_ATTRS_Pos 16
514 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos)
516 #define MPU_RASR_XN_Pos 28
517 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos)
519 #define MPU_RASR_AP_Pos 24
520 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos)
522 #define MPU_RASR_TEX_Pos 19
523 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos)
525 #define MPU_RASR_S_Pos 18
526 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos)
528 #define MPU_RASR_C_Pos 17
529 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos)
531 #define MPU_RASR_B_Pos 16
532 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos)
534 #define MPU_RASR_SRD_Pos 8
535 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos)
537 #define MPU_RASR_SIZE_Pos 1
538 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos)
540 #define MPU_RASR_ENABLE_Pos 0
541 #define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos)
544 #endif
545 
546 
563 /* Memory mapping of Cortex-M0+ Hardware */
564 #define SCS_BASE (0xE000E000UL)
565 #define SysTick_BASE (SCS_BASE + 0x0010UL)
566 #define NVIC_BASE (SCS_BASE + 0x0100UL)
567 #define SCB_BASE (SCS_BASE + 0x0D00UL)
569 #define SCB ((SCB_Type *) SCB_BASE )
570 #define SysTick ((SysTick_Type *) SysTick_BASE )
571 #define NVIC ((NVIC_Type *) NVIC_BASE )
573 #if (__MPU_PRESENT == 1)
574  #define MPU_BASE (SCS_BASE + 0x0D90UL)
575  #define MPU ((MPU_Type *) MPU_BASE )
576 #endif
577 
582 /*******************************************************************************
583  * Hardware Abstraction Layer
584  Core Function Interface contains:
585  - Core NVIC Functions
586  - Core SysTick Functions
587  - Core Register Access Functions
588  ******************************************************************************/
595 /* ########################## NVIC functions #################################### */
602 /* Interrupt Priorities are WORD accessible only under ARMv6M */
603 /* The following MACROS handle generation of the register offset and byte masks */
605 #define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
606 #define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
607 #define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
608 
617 {
618  NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
619 }
620 
621 
629 {
630  NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
631 }
632 
633 
645 {
646  return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
647 }
648 
649 
657 {
658  NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
659 }
660 
661 
669 {
670  NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
671 }
672 
673 
683 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
684 {
685  if(IRQn < 0) {
686  SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
687  (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
688  else {
689  NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
690  (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
691 }
692 
693 
706 {
707 
708  if(IRQn < 0) {
709  return((uint32_t)((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0+ system interrupts */
710  else {
711  return((uint32_t)((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
712 }
713 
714 
720 {
721  __DSB(); /* Ensure all outstanding memory accesses included
722  buffered write are completed before reset */
723  SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
725  __DSB(); /* Ensure completion of memory access */
726  while(1); /* wait until reset */
727 }
728 
733 /* ################################## SysTick function ############################################ */
740 #if (__Vendor_SysTickConfig == 0)
741 
757 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
758 {
759  if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
760 
761  SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */
762  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
763  SysTick->VAL = 0; /* Load the SysTick Counter Value */
766  SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
767  return (0); /* Function successful */
768 }
769 
770 #endif
771 
777 #endif /* __CORE_CM0PLUS_H_DEPENDANT */
778 
779 #endif /* __CMSIS_GENERIC */
780 
781 #ifdef __cplusplus
782 }
783 #endif
__STATIC_INLINE void __DSB(void)
Data Synchronization Barrier.
Definition: core_cmInstr.h:342
#define __STATIC_INLINE
Definition: core_cm0plus.h:78
#define SCB_AIRCR_SYSRESETREQ_Msk
Definition: core_cm0plus.h:382
static void NVIC_DisableIRQ(IRQn_Type IRQn)
Disable External Interrupt.
Definition: core_cm0plus.h:628
volatile uint32_t ICSR
Definition: core_cm0plus.h:307
Structure type to access the System Control Block (SCB).
Definition: core_cm0plus.h:304
volatile uint32_t LOAD
Definition: core_cm0plus.h:422
IRQn_Type
Definition: cmsis.h:60
#define __IO
Definition: core_cm0plus.h:167
#define SCB_AIRCR_VECTKEY_Pos
Definition: core_cm0plus.h:372
#define __I
Definition: core_cm0plus.h:164
Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Definition: core_cm0plus.h:279
volatile uint32_t CTRL
Definition: core_cm0plus.h:421
static uint32_t NVIC_GetPriority(IRQn_Type IRQn)
Get Interrupt Priority.
Definition: core_cm0plus.h:705
static void NVIC_EnableIRQ(IRQn_Type IRQn)
Enable External Interrupt.
Definition: core_cm0plus.h:616
#define SCB
Definition: core_cm0plus.h:569
static void NVIC_SystemReset(void)
System Reset.
Definition: core_cm0plus.h:719
#define SysTick_LOAD_RELOAD_Msk
Definition: core_cm0plus.h:442
#define __NVIC_PRIO_BITS
Definition: cmsis.h:54
static void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Set Interrupt Priority.
Definition: core_cm0plus.h:683
#define SysTick_CTRL_CLKSOURCE_Msk
Definition: core_cm0plus.h:432
#define SysTick_CTRL_TICKINT_Msk
Definition: core_cm0plus.h:435
volatile const uint32_t CALIB
Definition: core_cm0plus.h:424
volatile uint32_t VAL
Definition: core_cm0plus.h:423
Definition: cmsis.h:68
static void NVIC_SetPendingIRQ(IRQn_Type IRQn)
Set Pending Interrupt.
Definition: core_cm0plus.h:656
#define SysTick
Definition: core_cm0plus.h:570
#define NVIC
Definition: core_cm0plus.h:571
uint32_t w
Definition: core_cm0plus.h:211
#define SysTick_CTRL_ENABLE_Msk
Definition: core_cm0plus.h:438
Union type to access the Control Registers (CONTROL).
Definition: core_cm0plus.h:256
Union type to access the Application Program Status Register (APSR).
Definition: core_cm0plus.h:194
Union type to access the Interrupt Program Status Register (IPSR).
Definition: core_cm0plus.h:217
Union type to access the Special-Purpose Program Status Registers (xPSR).
Definition: core_cm0plus.h:230
Structure type to access the System Timer (SysTick).
Definition: core_cm0plus.h:419
volatile uint32_t CCR
Definition: core_cm0plus.h:315
volatile uint32_t AIRCR
Definition: core_cm0plus.h:313
volatile uint32_t SCR
Definition: core_cm0plus.h:314
volatile uint32_t SHCSR
Definition: core_cm0plus.h:318
static void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Clear Pending Interrupt.
Definition: core_cm0plus.h:668
volatile const uint32_t CPUID
Definition: core_cm0plus.h:306
static uint32_t SysTick_Config(uint32_t ticks)
System Tick Configuration.
Definition: core_cm0plus.h:757
static uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
Get Pending Interrupt.
Definition: core_cm0plus.h:644