NHS31xx SW API
chip.h
1 /*
2  * Copyright 2014-2020 NXP
3  * This software is owned or controlled by NXP and may only be used strictly
4  * in accordance with the applicable license terms. By expressly accepting
5  * such terms or by downloading, installing, activating and/or otherwise using
6  * the software, you are agreeing that you have read, and that you agree to
7  * comply with and are bound by, such license terms. If you do not agree to
8  * be bound by the applicable license terms, then you may not retain, install,
9  * activate or otherwise use the software.
10  */
11 
12 #ifndef __CHIP_H_
13 #define __CHIP_H_
14 
15 #include <stdint.h>
16 #include <stdbool.h>
17 #include <stddef.h>
18 #include "assert.h"
19 #include "cmsis.h"
20 #include "startup/startup.h"
21 #include "diag/diag.h"
22 
29 #define SDK_VERSION 12_4_nhs3100
31 #define NSS_SFRO_FREQUENCY 8000000
32 #define NSS_TFRO_FREQUENCY 32768
34 /* Memories */
35 #define EEPROM_START 0x30000000
36 #define EEPROM_ROW_SIZE 64
37 #define EEPROM_NR_OF_R_ROWS 64
38 #define EEPROM_NR_OF_RW_ROWS 58
40 #define FLASH_START 0
41 #define FLASH_SECTOR_SIZE 1024
42 #define FLASH_PAGE_SIZE 64
43 #define FLASH_PAGES_PER_SECTOR (FLASH_SECTOR_SIZE / FLASH_PAGE_SIZE)
44 #define FLASH_NR_OF_R_SECTORS 32
45 #define FLASH_NR_OF_RW_SECTORS 30
47 /* Base addresses of sample specific data */
48 #define NSS_NFC_UID_BASE (EEPROM_START + 0xF9C)
49 #define NSS_TSEN_CALIBRATION_TIMESTAMP (EEPROM_START + 0xFD4)
51 /* Base address of SW Peripherals */
52 #define NSS_IAP_ENTRY 0x1FFF1FF1
54 /* Base addresses of HW Peripherals */
55 #define NSS_I2C_BASE 0x40000000
56 #define NSS_WWDT_BASE 0x40004000
57 #define NSS_TIMER16_0_BASE 0x4000C000
58 #define NSS_TIMER32_0_BASE 0x40014000
59 #define NSS_FLASH_BASE 0x4003C000
60 #define NSS_EEPROM_BASE 0x40034000
61 #define NSS_PMU_BASE 0x40038000
62 #define NSS_SSP0_BASE 0x40040000
63 #define NSS_IOCON_BASE 0x40044000
64 #define NSS_SYSCON_BASE 0x40048000
65 #define NSS_RTC_BASE 0x40054000
66 #define NSS_NFC_BASE 0x40058000
67 #define NSS_TSEN_BASE 0x40060000
68 #define NSS_GPIO_BASE 0x50000000
70 /* Handles to HW Peripherals */
71 #define NSS_I2C ((NSS_I2C_T *) NSS_I2C_BASE)
72 #define NSS_WWDT ((NSS_WWDT_T *) NSS_WWDT_BASE)
73 #define NSS_TIMER16_0 ((NSS_TIMER_T *) NSS_TIMER16_0_BASE)
74 #define NSS_TIMER32_0 ((NSS_TIMER_T *) NSS_TIMER32_0_BASE)
75 #define NSS_FLASH ((NSS_FLASH_T *) NSS_FLASH_BASE)
76 #define NSS_EEPROM ((NSS_EEPROM_T*) NSS_EEPROM_BASE)
77 #define NSS_PMU ((NSS_PMU_T *) NSS_PMU_BASE)
78 #define NSS_SSP0 ((NSS_SSP_T *) NSS_SSP0_BASE)
79 #define NSS_IOCON ((NSS_IOCON_T *) NSS_IOCON_BASE)
80 #define NSS_SYSCON ((NSS_SYSCON_T*) NSS_SYSCON_BASE)
81 #define NSS_RTC ((NSS_RTC_T *) NSS_RTC_BASE)
82 #define NSS_NFC ((NSS_NFC_T *) NSS_NFC_BASE)
83 #define NSS_TSEN ((NSS_TSEN_T *) NSS_TSEN_BASE)
84 #define NSS_GPIO ((NSS_GPIO_T *) NSS_GPIO_BASE)
87 typedef struct NFC_UID_S {
88  uint8_t bytes[8];
89 } NFC_UID_T;
90 
97 #define NSS_NFC_UID ((NFC_UID_T *) NSS_NFC_UID_BASE)
98 
99 #include "bussync_nss.h"
100 #include "clock_nss.h"
101 #include "eeprom_nss.h"
102 #include "flash_nss.h"
103 #include "gpio_nss.h"
104 #include "i2c_nss.h"
105 #include "iap_nss.h"
106 #include "iocon_nss.h"
107 #include "nfc_nss.h"
108 #include "pmu_nss.h"
109 #include "rtc_nss.h"
110 #include "ssp_nss.h"
111 #include "syscon_nss.h"
112 #include "timer_nss.h"
113 #include "tsen_nss.h"
114 #include "wwdt_nss.h"
115 
116 /* Driver implementations with multiple instances */
117 #define Chip_TIMER16_0_Init() Chip_TIMER_Init(NSS_TIMER16_0, CLOCK_PERIPHERAL_16TIMER0)
118 #define Chip_TIMER16_0_DeInit() Chip_TIMER_DeInit(NSS_TIMER16_0, CLOCK_PERIPHERAL_16TIMER0)
119 #define Chip_TIMER32_0_Init() Chip_TIMER_Init(NSS_TIMER32_0, CLOCK_PERIPHERAL_32TIMER0)
120 #define Chip_TIMER32_0_DeInit() Chip_TIMER_DeInit(NSS_TIMER32_0, CLOCK_PERIPHERAL_32TIMER0)
130 #ifndef WEAK
131 #define WEAK __attribute__ ((weak))
132 #endif
133 
134 #endif
Definition: chip.h:87