NHS31xx SW API
core_cmInstr.h
1 /**************************************************************************/
24 #ifndef __CORE_CMINSTR_H
25 #define __CORE_CMINSTR_H
26 
27 
28 /* ########################## Core Instruction Access ######################### */
35 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
36 /* ARM armcc specific functions */
37 
38 #if (__ARMCC_VERSION < 400677)
39  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
40 #endif
41 
42 
47 #define __NOP __nop
48 
49 
55 #define __WFI __wfi
56 
57 
63 #define __WFE __wfe
64 
65 
70 #define __SEV __sev
71 
72 
79 #define __ISB() __isb(0xF)
80 
81 
87 #define __DSB() __dsb(0xF)
88 
89 
95 #define __DMB() __dmb(0xF)
96 
97 
105 #define __REV __rev
106 
107 
115 __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
116 {
117  rev16 r0, r0
118  bx lr
119 }
120 
121 
129 __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
130 {
131  revsh r0, r0
132  bx lr
133 }
134 
135 
144 #define __ROR __ror
145 
146 
147 #if (__CORTEX_M >= 0x03)
148 
156 #define __RBIT __rbit
157 
158 
166 #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
167 
168 
176 #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
177 
178 
186 #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
187 
188 
198 #define __STREXB(value, ptr) __strex(value, ptr)
199 
200 
210 #define __STREXH(value, ptr) __strex(value, ptr)
211 
212 
222 #define __STREXW(value, ptr) __strex(value, ptr)
223 
224 
230 #define __CLREX __clrex
231 
232 
241 #define __SSAT __ssat
242 
243 
252 #define __USAT __usat
253 
254 
262 #define __CLZ __clz
263 
264 #endif /* (__CORTEX_M >= 0x03) */
265 
266 
267 
268 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
269 /* IAR iccarm specific functions */
270 
271 #include <cmsis_iar.h>
272 
273 
274 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
275 /* TI CCS specific functions */
276 
277 #include <cmsis_ccs.h>
278 
279 
280 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
281 /* GNU gcc specific functions */
282 
287 __attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
288 {
289  __ASM volatile ("nop");
290 }
291 
292 
298 __attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
299 {
300  __ASM volatile ("wfi");
301 }
302 
303 
309 __attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
310 {
311  __ASM volatile ("wfe");
312 }
313 
314 
319 __attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
320 {
321  __ASM volatile ("sev");
322 }
323 
324 
331 __attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
332 {
333  __ASM volatile ("isb");
334 }
335 
336 
342 __attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
343 {
344  __ASM volatile ("dsb");
345 }
346 
347 
353 __attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
354 {
355  __ASM volatile ("dmb");
356 }
357 
358 
366 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
367 {
368  uint32_t result;
369 
370  __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
371  return(result);
372 }
373 
374 
382 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
383 {
384  uint32_t result;
385 
386  __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
387  return(result);
388 }
389 
390 
398 __attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
399 {
400  uint32_t result;
401 
402  __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
403  return(result);
404 }
405 
406 
415 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
416 {
417 
418  __ASM volatile ("ror %0, %0, %1" : "+r" (op1) : "r" (op2) );
419  return(op1);
420 }
421 
422 
423 #if (__CORTEX_M >= 0x03)
424 
432 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
433 {
434  uint32_t result;
435 
436  __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
437  return(result);
438 }
439 
440 
448 __attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
449 {
450  uint8_t result;
451 
452  __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
453  return(result);
454 }
455 
456 
464 __attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
465 {
466  uint16_t result;
467 
468  __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
469  return(result);
470 }
471 
472 
480 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
481 {
482  uint32_t result;
483 
484  __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
485  return(result);
486 }
487 
488 
498 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
499 {
500  uint32_t result;
501 
502  __ASM volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
503  return(result);
504 }
505 
506 
516 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
517 {
518  uint32_t result;
519 
520  __ASM volatile ("strexh %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
521  return(result);
522 }
523 
524 
534 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
535 {
536  uint32_t result;
537 
538  __ASM volatile ("strex %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
539  return(result);
540 }
541 
542 
548 __attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
549 {
550  __ASM volatile ("clrex");
551 }
552 
553 
562 #define __SSAT(ARG1,ARG2) \
563 ({ \
564  uint32_t __RES, __ARG1 = (ARG1); \
565  __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
566  __RES; \
567  })
568 
569 
578 #define __USAT(ARG1,ARG2) \
579 ({ \
580  uint32_t __RES, __ARG1 = (ARG1); \
581  __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
582  __RES; \
583  })
584 
585 
593 __attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
594 {
595  uint8_t result;
596 
597  __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
598  return(result);
599 }
600 
601 #endif /* (__CORTEX_M >= 0x03) */
602 
603 
604 
605 
606 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
607 /* TASKING carm specific functions */
608 
609 /*
610  * The CMSIS functions have been implemented as intrinsics in the compiler.
611  * Please use "carm -?i" to get an up to date list of all intrinsics,
612  * Including the CMSIS ones.
613  */
614 
615 #endif
616 
619 #endif /* __CORE_CMINSTR_H */
__STATIC_INLINE void __DSB(void)
Data Synchronization Barrier.
Definition: core_cmInstr.h:342
#define __STATIC_INLINE
Definition: core_cm0plus.h:78
__STATIC_INLINE void __SEV(void)
Send Event.
Definition: core_cmInstr.h:319
__STATIC_INLINE void __WFI(void)
Wait For Interrupt.
Definition: core_cmInstr.h:298
#define __ASM
Definition: core_cm0plus.h:76
__STATIC_INLINE void __DMB(void)
Data Memory Barrier.
Definition: core_cmInstr.h:353
__STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
Rotate Right in unsigned value (32 bit)
Definition: core_cmInstr.h:415
__STATIC_INLINE void __WFE(void)
Wait For Event.
Definition: core_cmInstr.h:309
__STATIC_INLINE void __NOP(void)
No Operation.
Definition: core_cmInstr.h:287
__STATIC_INLINE int32_t __REVSH(int32_t value)
Reverse byte order in signed short value.
Definition: core_cmInstr.h:398
__STATIC_INLINE uint32_t __REV16(uint32_t value)
Reverse byte order (16 bit)
Definition: core_cmInstr.h:382
__STATIC_INLINE uint32_t __REV(uint32_t value)
Reverse byte order (32 bit)
Definition: core_cmInstr.h:366
__STATIC_INLINE void __ISB(void)
Instruction Synchronization Barrier.
Definition: core_cmInstr.h:331