NHS31xx SW API
cmsis: Cortex-M0+ CMSIS support

Detailed Description

Provides an access layer to the functionality of the Cortex-M0+ core.
Please refer to Functions and Instructions Reference for all the available functions and to CMSIS Core Instruction Interface for all the available instructions.

Modules

 CMSIS CM0+ definitions
 
 CMSIS Core Instruction Interface
 
 Defines and Type Definitions
 
 Functions and Instructions Reference
 

Macros

#define __CM0_REV   0x0000
 
#define __MPU_PRESENT   0
 
#define __NVIC_PRIO_BITS   2
 
#define __Vendor_SysTickConfig   0
 

Enumerations

enum  IRQn_Type {
  Reset_IRQn = -15,
  NonMaskableInt_IRQn = -14,
  HardFault_IRQn = -13,
  SVCall_IRQn = -5,
  PendSV_IRQn = -2,
  SysTick_IRQn = -1,
  PIO0_0_IRQn = 0,
  PIO0_1_IRQn = 1,
  PIO0_2_IRQn = 2,
  PIO0_3_IRQn = 3,
  PIO0_4_IRQn = 4,
  PIO0_5_IRQn = 5,
  PIO0_6_IRQn = 6,
  PIO0_7_IRQn = 7,
  PIO0_8_IRQn = 8,
  PIO0_9_IRQn = 9,
  PIO0_10_IRQn = 10,
  RFFIELD_IRQn = 11,
  RTCPWREQ_IRQn = 12,
  NFC_IRQn = 13,
  RTC_IRQn = 14,
  I2C0_IRQn = 15,
  CT16B0_IRQn = 16,
  PMUFLD_IRQn = 17,
  CT32B0_IRQn = 18,
  PMUBOD_IRQn = 19,
  SSP0_IRQn = 20,
  TSEN_IRQn = 21,
  C2D_IRQn = 22,
  Reserved1_IRQn = 23,
  I2D_IRQn = 24,
  ADCDAC_IRQn = 25,
  WDT_IRQn = 26,
  FLASH_IRQn = 27,
  EEPROM_IRQn = 28,
  Reserved2_IRQn = 29,
  Reserved3_IRQn = 30,
  PIO0_IRQn = 31
}
 

Macro Definition Documentation

◆ __CM0_REV

#define __CM0_REV   0x0000

Cortex-M0 Core Revision

◆ __MPU_PRESENT

#define __MPU_PRESENT   0

MPU present or not

◆ __NVIC_PRIO_BITS

#define __NVIC_PRIO_BITS   2

Number of Bits used for Priority Levels

◆ __Vendor_SysTickConfig

#define __Vendor_SysTickConfig   0

Set to 1 if different SysTick Config is used

Enumeration Type Documentation

◆ IRQn_Type

enum IRQn_Type

Defines the supported NVIC Peripheral interrupts

Enumerator
Reset_IRQn 

1 Reset Vector, invoked on Power up and warm reset

NonMaskableInt_IRQn 

2 Non Maskable Interrupt

HardFault_IRQn 

3 Cortex-M0+ Hard Fault Interrupt

SVCall_IRQn 

11 Cortex-M0+ SV Call Interrupt

PendSV_IRQn 

14 Cortex-M0+ Pend SV Interrupt

SysTick_IRQn 

15 Cortex-M0+ System Tick Interrupt

PIO0_0_IRQn 

PIO0_0 Start Logic Interrupt

PIO0_1_IRQn 

PIO0_1 Start Logic Interrupt

PIO0_2_IRQn 

PIO0_2 Start Logic Interrupt

PIO0_3_IRQn 

PIO0_3 Start Logic Interrupt

PIO0_4_IRQn 

PIO0_4 Start Logic Interrupt

PIO0_5_IRQn 

PIO0_5 Start Logic Interrupt

PIO0_6_IRQn 

PIO0_6 Start Logic Interrupt

PIO0_7_IRQn 

PIO0_7 Start Logic Interrupt

PIO0_8_IRQn 

PIO0_8 Start Logic Interrupt

PIO0_9_IRQn 

PIO0_9 Start Logic Interrupt

PIO0_10_IRQn 

PIO0_10 Start Logic Interrupt

RFFIELD_IRQn 

NFC Access Start Logic Interrupt

RTCPWREQ_IRQn 

RTC Wakeup Request Start Logic Interrupt

NFC_IRQn 

NFC Read/Write Interrupt

RTC_IRQn 

RTC Wakeup Interrupt

I2C0_IRQn 

I2C0 Interrupt

CT16B0_IRQn 

16-bit Timer 0 Interrupt

PMUFLD_IRQn 

RF Power Detection Interrupt

CT32B0_IRQn 

32-bit Timer 0 Interrupt

PMUBOD_IRQn 

Brown Out Detection Interrupt

SSP0_IRQn 

SSP0 Interrupt

TSEN_IRQn 

Temperature Sensor Interrupt

C2D_IRQn 

Capacitance-to-Digital converter Interrupt

Reserved1_IRQn 

reserved

I2D_IRQn 

Current-to-Digital converter Interrupt

ADCDAC_IRQn 

Analog-to-Digital/Digital-to-Analog converter Interrupt

WDT_IRQn 

Watchdog Timer Interrupt

FLASH_IRQn 

FLASH memory Interrupt

EEPROM_IRQn 

EEPROM memory Interrupt

Reserved2_IRQn 

reserved

Reserved3_IRQn 

reserved

PIO0_IRQn 

GPIO Port 0 Interrupt