NHS31xx SW API
iocon: IO Configuration driver

Detailed Description

This driver select the peripheral IO (PIO) pin function of digital pins (e.g. PIO or I2C clock) and analog pins. The characteristics include peripheral function, analog pins functionality, GPIO and its electrical modes (e.g. pull-up or pull-down), the low-pass input filter modes, and current drive output mode of all pins. In addition, the I2C-bus pins can be configured for different I2C-bus modes.

The pin function determine the peripheral function of a pin, and with that the direction. For example, if the pins are configured as GPIO pins, the Chip_GPIO_SetPortDIR of GPIO driver determine whether the pin is configured as an input or output. For other peripheral function, the pin direction is controlled automatically depending on the pin's functionality.

The pin resistor modes allow enabling of on-chip pull-up or pull-down resistors or to select the repeater mode. The repeater mode enables the pull-up resistor if the pin is at a logic HIGH and enables the pull-down resistor if the pin is at a logic LOW. This causes the pin to retain its last known state if it is configured as an input and is not driven externally. The state retention is not applicable to the Deep power-down mode. Repeater mode may typically be used to prevent a pin from floating (and potentially using significant power if it floats to an indeterminate state) if it is temporarily not driven.

I2C function mode:
If the I2C function is selected by the pin function (for designated pins), then the I2C-bus pins can be configured for two I2C-modes:
  1. Standard mode/Fast-mode I2C with input glitch filter (this includes an open-drain output according to the I2C-bus specification).
  2. Standard open-drain I/O functionality without input filter.
The I2C pads have no pull-up / pull down functionality.

Current Drive Capabilities:
Some pins have high current drive output capabilities (up to 20 mA when VDD is 1.8V) to the load. See user manual for pins with such capabilities. These PIO pins can be set to either digital mode or current drive mode.
Analog Functionality:
The analog input pins (IOCON_ANA0_*) have direct analog connections to the external analog busses, and are protected by the ESD structures. The pin function determines the interconnections, e.g. to VSS or to associated analog bus. Refer to user manual for pin specific functions.

Analog Bus Grounding:
This feature allows the internal grounding of the analog busses. The chip has analog buses that connect the respective pin to the muxes of the analog blocks (ADCDAC, I2D, C2D). All these buses are grounded by default. During operation of analog blocks (ADCDAC, I2D, C2D), analog bus(es) must be ungrounded. This is ensured by usage of Chip_IOCON_SetPinConfig or by the respective analog block driver in its Chip_*_SetMux* function.
Warning
If the analog bus is no longer used, it is the responsibility of the application to ground it again using the Chip_IOCON_GroundAnabus (not doing so might impact the accuracy of the analog block(s)).
Example 1 - Configuring pins
  • PIO0_0 as GPIO with no pull-up/down and LPF disabled
  • PIO0_1 as GPIO with pull-up and LPF enabled
  • PIO0_2 as peripheral function 1 (see user manual for respective modes)
  • PIO0_3 as high current drive mode, with no pull-up/down LPF disabled, output low current of 4mA and output high current of 16mA
  • PIO0_4 as I2C peripheral function, standard or fast I2C mode

Data Structures

struct  NSS_IOCON_T
 

Macros

#define IOCON_FUNC_0   (0x0)
 
#define IOCON_FUNC_1   (0x1)
 
#define IOCON_FUNC_2   (0x2)
 
#define IOCON_FUNC_3   (0x3)
 
#define IOCON_FUNC_4   (0x4)
 
#define IOCON_FUNC_5   (0x5)
 
#define IOCON_FUNC_6   (0x6)
 
#define IOCON_FUNC_7   (0x7)
 
#define IOCON_FUNC_MASK   (0x7)
 
#define IOCON_RMODE_INACT   (0x0 << 3)
 
#define IOCON_RMODE_PULLDOWN   (0x1 << 3)
 
#define IOCON_RMODE_PULLUP   (0x2 << 3)
 
#define IOCON_RMODE_REPEATER   (0x3 << 3)
 
#define IOCON_RMODE_MASK   (0x3 << 3)
 
#define IOCON_LPF_DISABLE   (0x0 << 5)
 
#define IOCON_LPF_ENABLE   (0x1 << 5)
 
#define IOCON_LPF_MASK   (0x1 << 5)
 
#define IOCON_CDRIVE_FIXEDVOLTAGE   (0x0 << 6)
 
#define IOCON_CDRIVE_PROGRAMMABLECURRENT   (0x1 << 6)
 
#define IOCON_CDRIVE_MASK   (0x1 << 6)
 
#define IOCON_DDRIVE_HIGH   (0x0 << 7)
 
#define IOCON_DDRIVE_ULTRAHIGH   (0x1 << 7)
 
#define IOCON_DDRIVE_MASK   (0x1 << 7)
 
#define IOCON_I2CMODE_STDFAST   (0x0 << 8)
 
#define IOCON_I2CMODE_PIO   (0x1 << 8)
 
#define IOCON_I2CMODE_MASK   (0x1 << 8)
 
#define IOCON_ILO_VAL(x)   (((x) & 0xFF) << 8 )
 
#define IOCON_IHI_VAL(x)   (((x) & 0xFF) << 16)
 
#define IOCON_ILO_MASK   (0xFF << 8)
 
#define IOCON_IHI_MASK   (0xFF << 16)
 

Enumerations

enum  IOCON_PIN_T {
  IOCON_PIO0_0 = (0x000 >> 2),
  IOCON_PIO0_1 = (0x004 >> 2),
  IOCON_PIO0_2 = (0x008 >> 2),
  IOCON_PIO0_3 = (0x00C >> 2),
  IOCON_PIO0_4 = (0x010 >> 2),
  IOCON_PIO0_5 = (0x014 >> 2),
  IOCON_PIO0_6 = (0x018 >> 2),
  IOCON_PIO0_7 = (0x01C >> 2),
  IOCON_PIO0_8 = (0x020 >> 2),
  IOCON_PIO0_9 = (0x024 >> 2),
  IOCON_PIO0_10 = (0x028 >> 2),
  IOCON_PIO0_11 = (0x02C >> 2),
  IOCON_ANA0_0 = (0x030 >> 2),
  IOCON_ANA0_1 = (0x034 >> 2),
  IOCON_ANA0_2 = (0x038 >> 2),
  IOCON_ANA0_3 = (0x03C >> 2),
  IOCON_ANA0_4 = (0x040 >> 2),
  IOCON_ANA0_5 = (0x044 >> 2),
  IOCON_ANA0_6 = (0x048 >> 2),
  IOCON_ANA0_7 = (0x04C >> 2),
  IOCON_ANA0_8 = (0x050 >> 2),
  IOCON_ANA0_9 = (0x054 >> 2),
  IOCON_ANA0_10 = (0x058 >> 2),
  IOCON_ANA0_11 = (0x05C >> 2)
}
 
enum  IOCON_ANABUS_T {
  IOCON_ANABUS_EXT0 = (1 << 0),
  IOCON_ANABUS_EXT1 = (1 << 1),
  IOCON_ANABUS_EXT2 = (1 << 2),
  IOCON_ANABUS_EXT3 = (1 << 3),
  IOCON_ANABUS_EXT4 = (1 << 4),
  IOCON_ANABUS_EXT5 = (1 << 5),
  IOCON_ANABUS_EXT6 = (1 << 6),
  IOCON_ANABUS_EXT7 = (1 << 7),
  IOCON_ANABUS_EXT8 = (1 << 8),
  IOCON_ANABUS_EXT9 = (1 << 9),
  IOCON_ANABUS_EXT10 = (1 << 10),
  IOCON_ANABUS_EXT11 = (1 << 11),
  IOCON_ANABUS_INT0 = (1 << 12),
  IOCON_ANABUS_INT1 = (1 << 13),
  IOCON_ANABUS_INT2 = (1 << 14),
  IOCON_ANABUS_INT3 = (1 << 15),
  IOCON_ANABUS_INT4 = (1 << 16),
  IOCON_ANABUS_INT5 = (1 << 17),
  IOCON_ANABUS_INT6 = (1 << 18),
  IOCON_ANABUS_INT7 = (1 << 19),
  IOCON_ANABUS_INT8 = (1 << 20),
  IOCON_ANABUS_INT9 = (1 << 21),
  IOCON_ANABUS_INT10 = (1 << 22),
  IOCON_ANABUS_INT11 = (1 << 23),
  IOCON_ANABUS_INT12 = (1 << 24),
  IOCON_ANABUS_INT13 = (1 << 25),
  IOCON_ANABUS_INT14 = (1 << 26),
  IOCON_ANABUS_INT15 = (1 << 27)
}
 

Functions

void Chip_IOCON_Init (NSS_IOCON_T *pIOCON)
 
void Chip_IOCON_DeInit (NSS_IOCON_T *pIOCON)
 
void Chip_IOCON_SetPinConfig (NSS_IOCON_T *pIOCON, IOCON_PIN_T pin, int config)
 
int Chip_IOCON_GetPinConfig (NSS_IOCON_T *pIOCON, IOCON_PIN_T pin)
 
void Chip_IOCON_SetAnabusGrounded (NSS_IOCON_T *pIOCON, IOCON_ANABUS_T bitvector)
 
IOCON_ANABUS_T Chip_IOCON_GetAnabusGrounded (NSS_IOCON_T *pIOCON)
 
void Chip_IOCON_GroundAnabus (NSS_IOCON_T *pIOCON, IOCON_ANABUS_T bitvector)
 
void Chip_IOCON_UngroundAnabus (NSS_IOCON_T *pIOCON, IOCON_ANABUS_T bitvector)
 

Data Structure Documentation

◆ NSS_IOCON_T

struct NSS_IOCON_T

NSS IOCON register block structure

Data Fields
__IO uint32_t REG[24]

12 digital pins and 12 analog pins.

__IO uint32_t RESERVED0[8]
__IO uint32_t ANABUSGROUND

Analog bus grounding control.

Macro Definition Documentation

◆ IOCON_FUNC_0

#define IOCON_FUNC_0   (0x0)

Selects pin function 0

◆ IOCON_FUNC_1

#define IOCON_FUNC_1   (0x1)

Selects pin function 1

◆ IOCON_FUNC_2

#define IOCON_FUNC_2   (0x2)

Selects pin function 2

◆ IOCON_FUNC_3

#define IOCON_FUNC_3   (0x3)

Selects pin function 3

◆ IOCON_FUNC_4

#define IOCON_FUNC_4   (0x4)

Selects pin function 4

◆ IOCON_FUNC_5

#define IOCON_FUNC_5   (0x5)

Selects pin function 5

◆ IOCON_FUNC_6

#define IOCON_FUNC_6   (0x6)

Selects pin function 6

◆ IOCON_FUNC_7

#define IOCON_FUNC_7   (0x7)

Selects pin function 7

◆ IOCON_FUNC_MASK

#define IOCON_FUNC_MASK   (0x7)

Pin function mask

◆ IOCON_RMODE_INACT

#define IOCON_RMODE_INACT   (0x0 << 3)

No addition resistor pin function

◆ IOCON_RMODE_PULLDOWN

#define IOCON_RMODE_PULLDOWN   (0x1 << 3)

Selects pull-down resistor function

◆ IOCON_RMODE_PULLUP

#define IOCON_RMODE_PULLUP   (0x2 << 3)

Selects pull-up resistor function

◆ IOCON_RMODE_REPEATER

#define IOCON_RMODE_REPEATER   (0x3 << 3)

Selects pin repeater function

◆ IOCON_RMODE_MASK

#define IOCON_RMODE_MASK   (0x3 << 3)

Selects pin resistor mode mask

◆ IOCON_LPF_DISABLE

#define IOCON_LPF_DISABLE   (0x0 << 5)

Disables Low pass filter

◆ IOCON_LPF_ENABLE

#define IOCON_LPF_ENABLE   (0x1 << 5)

Enables Low pass filter

◆ IOCON_LPF_MASK

#define IOCON_LPF_MASK   (0x1 << 5)

Selects pin LPF mask

◆ IOCON_CDRIVE_FIXEDVOLTAGE

#define IOCON_CDRIVE_FIXEDVOLTAGE   (0x0 << 6)

Programmable current driver - Fixed Voltage driver

◆ IOCON_CDRIVE_PROGRAMMABLECURRENT

#define IOCON_CDRIVE_PROGRAMMABLECURRENT   (0x1 << 6)

Programmable current driver - Programmable current driver

◆ IOCON_CDRIVE_MASK

#define IOCON_CDRIVE_MASK   (0x1 << 6)

Selects pin current drive mask

◆ IOCON_DDRIVE_HIGH

#define IOCON_DDRIVE_HIGH   (0x0 << 7)

Digital drive strength - High Drive (20mA drive at 3.1V supply)

◆ IOCON_DDRIVE_ULTRAHIGH

#define IOCON_DDRIVE_ULTRAHIGH   (0x1 << 7)

Digital drive strength - Ultra-high drive (20mA drive at 2.4V supply)

◆ IOCON_DDRIVE_MASK

#define IOCON_DDRIVE_MASK   (0x1 << 7)

Selects pin digital drive mask

◆ IOCON_I2CMODE_STDFAST

#define IOCON_I2CMODE_STDFAST   (0x0 << 8)

I2C Standard mode or fast-mode

◆ IOCON_I2CMODE_PIO

#define IOCON_I2CMODE_PIO   (0x1 << 8)

Standard I/O functionality

◆ IOCON_I2CMODE_MASK

#define IOCON_I2CMODE_MASK   (0x1 << 8)

Selects pin I2C mode mask

◆ IOCON_ILO_VAL

#define IOCON_ILO_VAL (   x)    (((x) & 0xFF) << 8 )

Set CDRIVE Low Value

◆ IOCON_IHI_VAL

#define IOCON_IHI_VAL (   x)    (((x) & 0xFF) << 16)

Set CDRIVE High value

◆ IOCON_ILO_MASK

#define IOCON_ILO_MASK   (0xFF << 8)

Set CDRIVE Low mask

◆ IOCON_IHI_MASK

#define IOCON_IHI_MASK   (0xFF << 16)

Set CDRIVE High mask

Enumeration Type Documentation

◆ IOCON_PIN_T

I/O Pins Definitions

Enumerator
IOCON_PIO0_0 

Represents the digital pin 0

IOCON_PIO0_1 

Represents the digital pin 1

IOCON_PIO0_2 

Represents the digital pin 2

IOCON_PIO0_3 

Represents the digital pin 3

IOCON_PIO0_4 

Represents the digital pin 4

IOCON_PIO0_5 

Represents the digital pin 5

IOCON_PIO0_6 

Represents the digital pin 6

IOCON_PIO0_7 

Represents the digital pin 7

IOCON_PIO0_8 

Represents the digital pin 8

IOCON_PIO0_9 

Represents the digital pin 9

IOCON_PIO0_10 

Represents the digital pin 10

IOCON_PIO0_11 

Represents the digital pin 11

IOCON_ANA0_0 

Represents the analog pin 0

IOCON_ANA0_1 

Represents the analog pin 1

IOCON_ANA0_2 

Represents the analog pin 2

IOCON_ANA0_3 

Represents the analog pin 3

IOCON_ANA0_4 

Represents the analog pin 4

IOCON_ANA0_5 

Represents the analog pin 5

IOCON_ANA0_6 

Represents the analog pin 6

IOCON_ANA0_7 

Represents the analog pin 7

IOCON_ANA0_8 

Represents the analog pin 8

IOCON_ANA0_9 

Represents the analog pin 9

IOCON_ANA0_10 

Represents the analog pin 10

IOCON_ANA0_11 

Represents the analog pin 11

◆ IOCON_ANABUS_T

Analog Bus Definitions

Enumerator
IOCON_ANABUS_EXT0 

Represents the ana_extbus0

IOCON_ANABUS_EXT1 

Represents the ana_extbus1

IOCON_ANABUS_EXT2 

Represents the ana_extbus2

IOCON_ANABUS_EXT3 

Represents the ana_extbus3

IOCON_ANABUS_EXT4 

Represents the ana_extbus4

IOCON_ANABUS_EXT5 

Represents the ana_extbus5

IOCON_ANABUS_EXT6 

Represents the ana_extbus6

IOCON_ANABUS_EXT7 

Represents the ana_extbus7

IOCON_ANABUS_EXT8 

Represents the ana_extbus8

IOCON_ANABUS_EXT9 

Represents the ana_extbus9

IOCON_ANABUS_EXT10 

Represents the ana_extbus10

IOCON_ANABUS_EXT11 

Represents the ana_extbus11

IOCON_ANABUS_INT0 

Represents the ana_intbus0

IOCON_ANABUS_INT1 

Represents the ana_intbus1

IOCON_ANABUS_INT2 

Represents the ana_intbus2

IOCON_ANABUS_INT3 

Represents the ana_intbus3

IOCON_ANABUS_INT4 

Represents the ana_intbus4

IOCON_ANABUS_INT5 

Represents the ana_intbus5

IOCON_ANABUS_INT6 

Represents the ana_intbus6

IOCON_ANABUS_INT7 

Represents the ana_intbus7

IOCON_ANABUS_INT8 

Represents the ana_intbus8

IOCON_ANABUS_INT9 

Represents the ana_intbus9

IOCON_ANABUS_INT10 

Represents the ana_intbus10

IOCON_ANABUS_INT11 

Represents the ana_intbus11

IOCON_ANABUS_INT12 

Represents the ana_intbus12

IOCON_ANABUS_INT13 

Represents the ana_intbus13

IOCON_ANABUS_INT14 

Represents the ana_intbus14

IOCON_ANABUS_INT15 

Represents the ana_intbus15

Function Documentation

◆ Chip_IOCON_Init()

void Chip_IOCON_Init ( NSS_IOCON_T pIOCON)

Initialize IOCON block

Parameters
pIOCON: The base address of the IOCON peripheral on the chip

◆ Chip_IOCON_DeInit()

void Chip_IOCON_DeInit ( NSS_IOCON_T pIOCON)

De-Initialize IOCON block

Parameters
pIOCON: The base address of the IOCON peripheral on the chip

◆ Chip_IOCON_SetPinConfig()

void Chip_IOCON_SetPinConfig ( NSS_IOCON_T pIOCON,
IOCON_PIN_T  pin,
int  config 
)

Sets I/O pin configuration

Parameters
pIOCON: The base address of the IOCON peripheral on the chip
pin: GPIO pin to configure
config: I/O pin configuration. Use or'ed values defined by IOCON_* macros
Note
This function ungrounds the respective analog bus, if an analog pin is configured to be connected to analog bus. Refer to Analog Bus Grounding.
Warning
Special care must be taken when changing the pin function for the SWD pins. Once one or both of the SWD pins have been changed to a function other than SWD, it is not possible to start or continue a debug session. When this is done immediately after booting, it might never be possible to start a debug session with the IC anymore. See SW Debug Considerations for more details.

◆ Chip_IOCON_GetPinConfig()

int Chip_IOCON_GetPinConfig ( NSS_IOCON_T pIOCON,
IOCON_PIN_T  pin 
)

Gets I/O pin configuration

Parameters
pIOCON: The base address of the IOCON peripheral on the chip
pin: GPIO pin to retrieve the configuration from
Returns
The respective I/O pin configuration. Composed by or'ed values defined by IOCON_* macros, to be analyzed with IOCON_FUNC_MASK, IOCON_RMODE_MASK, IOCON_LPF_MASK, IOCON_CDRIVE_MASK, IOCON_DDRIVE_MASK, IOCON_I2CMODE_MASK, IOCON_ILO_MASK and IOCON_IHI_MASK

◆ Chip_IOCON_SetAnabusGrounded()

void Chip_IOCON_SetAnabusGrounded ( NSS_IOCON_T pIOCON,
IOCON_ANABUS_T  bitvector 
)

Grounds/UnGrounds the analog bus(es) described in IOCON_ANABUS_T

Parameters
pIOCON: The base address of the IOCON peripheral on the chip
bitvector: Bitvector of the analog bus(es) which are to be grounded/ungrounded
Note
This setting overwrites the existing setting for all the analog buses described in IOCON_ANABUS_T.
If the respective bit is set, the analog bus will be grounded, otherwise it will be ungrounded.
This functionality is overlapped with Chip_IOCON_GroundAnabus and Chip_IOCON_UngroundAnabus functions.

◆ Chip_IOCON_GetAnabusGrounded()

IOCON_ANABUS_T Chip_IOCON_GetAnabusGrounded ( NSS_IOCON_T pIOCON)

Retrieves a bitvector stating the grounded/ungrounded analog buses described in IOCON_ANABUS_T

Parameters
pIOCON: The base address of the IOCON peripheral on the chip
Returns
Bitvector stating the grounded/ungrounded analog buses
Note
If the respective bit is set, the analog bus is grounded, otherwise it is ungrounded.
All analog buses are grounded by default.

◆ Chip_IOCON_GroundAnabus()

void Chip_IOCON_GroundAnabus ( NSS_IOCON_T pIOCON,
IOCON_ANABUS_T  bitvector 
)

Grounds the required analog bus(es).

Parameters
pIOCON: The base address of the IOCON peripheral on the chip
bitvector: Bitvector of the analog bus(es) which needs to be grounded
Note
All analog buses are grounded by default.
Only the analog bus(es) set in bitvector are changed. All the others are left untouched.
Warning
Grounding of analog bus has to be taken care by application. Refer to Analog Bus Grounding.

◆ Chip_IOCON_UngroundAnabus()

void Chip_IOCON_UngroundAnabus ( NSS_IOCON_T pIOCON,
IOCON_ANABUS_T  bitvector 
)

Ungrounds the required analog bus(es).

Parameters
pIOCON: The base address of the IOCON peripheral on the chip
bitvector: Bitvector of the analog bus(es) which needs to be ungrounded
Note
All analog buses are grounded by default.
Only the analog bus(es) set in bitvector are changed. All the others are left untouched.