NHS31xx SW API
ssp: Serial Peripheral Interface / Synchronous Serial Port controller

Detailed Description

This driver provides APIs for the configuration and operation of the SSP hardware block. The SSP interface provides four operating modes:

  1. master/slave transmitter mode (polling)
  2. master/slave receiver mode (polling)
  3. master/slave simultaneous transmitter and receiver mode (polling)
  4. master/slave simultaneous transmitter and receiver mode (interrupt)

The SSP Driver supports data transfer on SPI, 4-wire SSI or Microwire buses. There can be multiple masters and slaves on the bus, though only one master and slave can communicate with each other at a given point in time. The SSP hardware block supports full-duplex data transfer of frames of length 4 bits to 16 bits. The driver supports both polled or interrupt based operation. Refer Polling Mode Usage for polling mode usage and Interrupt Mode Usage for interrupt mode usage

IOCON configuration for SSP:
The SSP-bus pins (IOCON_PIO0_2, IOCON_PIO0_6, IOCON_PIO0_8 and IOCON_PIO0_9) must be configured for the SSP (IOCON_FUNC_1). See IO Configuration driver iocon: IO Configuration driver for details.

SSP Clock rates:
The maximum allowed SSP clock rate in master or slave mode at a particular system clock can be referred from SW Clock Restrictions. SSP bitrate (when operating as a Master) can be set using the API Chip_SSP_SetBitRate. The resulting SSP bitrate is determined based on the values of 2 pre-scalers. The API Chip_SSP_SetBitRate internally calculates and sets the most appropriate pre-scaler values to achieve the closest bitrate lower or equal to the one that was requested. The first pre-scaler (P1) divides the SSP clock by an even value between 2 and 254. The second pre-scaler (P2) further divides the resultant clock by a value between 1 and 256. The resultant SSP clock rate can be obtained by using the API Chip_SSP_GetBitRate after setting a certain required bitrate using Chip_SSP_SetBitRate.
Note
During driver initialization (Chip_SSP_Init), there is no implicit check that the system clock/bitrate combination meets the clock restriction requirements. It is up to the caller to ensure that the respective restrictions are met.
During driver initialization (Chip_SSP_Init), the SSP clock divisor which determines the SSP clock is set to the same value as the system clock divisor to prevent synchronization issues. The user needs to take care of this in case the system clock is changed after driver initialization.
To use this driver:
SSP Driver is initialized as follows:
  1. SSP pin functions are configured using Chip_IOCON_SetPinConfig. IOCON driver needs to be initialized before this using Chip_IOCON_Init.
  2. SSP driver is initialized using Chip_SSP_Init. The initialization sequence configures the chip to master mode and sets the default values for frame length (SSP_BITS_8), frame format (SSP_FRAME_FORMAT_SPI), clock mode (SSP_CLOCK_CPHA0_CPOL0) and bitrate (100kbps).
  3. Reconfigure master/slave mode using Chip_SSP_SetMaster if applicable
  4. Reconfigure frame length, frame format and clock mode using Chip_SSP_SetFormat if applicable
  5. Reconfigure bitrate using Chip_SSP_SetBitRate if applicable
For SSP Master/Slave transmission or reception (polling):
  1. Initialize the SSP driver for master/slave mode as given in SSP Driver Initialisation
  2. Use one of the appropriate transfer API based on the type of transfer required.
For SSP Master/Slave simultaneous transmission and reception mode (polling):
  1. Initialize the SSP driver for master/slave mode as given in SSP Driver Initialisation
  2. Fill in Chip_SSP_DATA_SETUP_T structure
  3. Use Chip_SSP_RWFrames_Blocking API to complete the transfer
For SSP Master/Slave simultaneous transmission and reception mode (using interrupts):
  1. Initialize the SSP driver for master/slave mode as given in SSP Driver Initialisation
  2. Fill in Chip_SSP_DATA_SETUP_T structure
  3. Enable the SSP interrupt using Chip_SSP_Int_Enable
  4. Enable the SSP interrupt in NVIC using NVIC_EnableIRQ.
  5. Now the transmission can be done inside the interrupt handler using Chip_SSP_Int_RWFrames8Bits or Chip_SSP_Int_RWFrames16Bits APIs. need to be called inside the interrupt handler as well.
  6. In application main, wait till transmit FIFO is empty using Chip_SSP_GetStatus
Example 1 - Simultaneous master transmission and reception (polling)
Note
User can select appropriate System and SSP clocks as mentioned at SSP clock rates.
Example 2 - Simultaneous slave transmission and reception (interrupt)
Tx and Rx buffers, setup data structure and transfer completion status flag:
/* Initialise rx/tx setup data structure */
uint8_t tx[16];
uint8_t rx[16];
.tx_cnt = 0,
.length = sizeof(tx),
.rx_data = rx,
.tx_data = tx};
Setup and transfer of data: SSP Interrupt Handler:
((setup.rx_cnt >= setup.length) && (setup.tx_cnt >= setup.length))) {
}

Data Structures

struct  NSS_SSP_T
 
struct  Chip_SSP_DATA_SETUP_T
 

Macros

#define SSP_CR0_DSS(n)   ((uint32_t) ((n) & 0xF))
 
#define SSP_CR0_FRF_SPI   ((uint32_t) (0 << 4))
 
#define SSP_CR0_FRF_TI   ((uint32_t) (1 << 4))
 
#define SSP_CR0_FRF_MICROWIRE   ((uint32_t) (2 << 4))
 
#define SSP_CR0_CPOL_LO   ((uint32_t) (0))
 
#define SSP_CR0_CPOL_HI   ((uint32_t) (1 << 6))
 
#define SSP_CR0_CPHA_FIRST   ((uint32_t) (0))
 
#define SSP_CR0_CPHA_SECOND   ((uint32_t) (1 << 7))
 
#define SSP_CR0_SCR(n)   ((uint32_t) ((n & 0xFF) << 8))
 
#define SSP_CR0_BITMASK   ((uint32_t) (0xFFFF))
 
#define SSP_CR1_LBM_EN   ((uint32_t) (1 << 0))
 
#define SSP_CR1_SSP_EN   ((uint32_t) (1 << 1))
 
#define SSP_CR1_SLAVE_EN   ((uint32_t) (1 << 2))
 
#define SSP_CR1_MASTER_EN   ((uint32_t) (0))
 
#define SSP_CR1_SO_DISABLE   ((uint32_t) (1 << 3))
 
#define SSP_CR1_BITMASK   ((uint32_t) (0x0F))
 
#define SSP_CPSR_BITMASK   ((uint32_t) (0xFF))
 
#define SSP_DR_BITMASK(n)   ((n) & 0xFFFF)
 
#define SSP_SR_BITMASK   ((uint32_t) (0x1F))
 
#define SSP_ICR_BITMASK   ((uint32_t) (0x03))
 

Enumerations

enum  SSP_INT_STATUS_T {
  RESET = 0,
  SET = !RESET
}
 
enum  Status {
  ERROR = 0,
  SUCCESS = !ERROR
}
 
enum  SSP_STATUS_T {
  SSP_STAT_TFE = ((uint32_t)(1 << 0)),
  SSP_STAT_TNF = ((uint32_t)(1 << 1)),
  SSP_STAT_RNE = ((uint32_t)(1 << 2)),
  SSP_STAT_RFF = ((uint32_t)(1 << 3)),
  SSP_STAT_BSY = ((uint32_t)(1 << 4))
}
 
enum  SSP_INTMASK_T {
  SSP_RORIM = ((uint32_t)(1 << 0)),
  SSP_RTIM = ((uint32_t)(1 << 1)),
  SSP_RXIM = ((uint32_t)(1 << 2)),
  SSP_TXIM = ((uint32_t)(1 << 3)),
  SSP_INT_MASK_BITMASK = ((uint32_t)(0xF))
}
 
enum  SSP_MASKINTSTATUS_T {
  SSP_RORMIS = ((uint32_t)(1 << 0)),
  SSP_RTMIS = ((uint32_t)(1 << 1)),
  SSP_RXMIS = ((uint32_t)(1 << 2)),
  SSP_TXMIS = ((uint32_t)(1 << 3)),
  SSP_MASK_INT_STAT_BITMASK = ((uint32_t)(0xF))
}
 
enum  SSP_RAWINTSTATUS_T {
  SSP_RORRIS = ((uint32_t)(1 << 0)),
  SSP_RTRIS = ((uint32_t)(1 << 1)),
  SSP_RXRIS = ((uint32_t)(1 << 2)),
  SSP_TXRIS = ((uint32_t)(1 << 3)),
  SSP_RAW_INT_STAT_BITMASK = ((uint32_t)(0xF))
}
 
enum  SSP_INTCLEAR_T {
  SSP_RORIC = 0x0,
  SSP_RTIC = 0x1,
  SSP_INT_CLEAR_BITMASK = 0x3
}
 
enum  CHIP_SSP_CLOCK_MODE_T {
  SSP_CLOCK_CPHA0_CPOL0 = (0 << 6),
  SSP_CLOCK_CPHA0_CPOL1 = (1u << 6),
  SSP_CLOCK_CPHA1_CPOL0 = (2u << 6),
  SSP_CLOCK_CPHA1_CPOL1 = (3u << 6),
  SSP_CLOCK_MODE0 = SSP_CLOCK_CPHA0_CPOL0,
  SSP_CLOCK_MODE1 = SSP_CLOCK_CPHA1_CPOL0,
  SSP_CLOCK_MODE2 = SSP_CLOCK_CPHA0_CPOL1,
  SSP_CLOCK_MODE3 = SSP_CLOCK_CPHA1_CPOL1
}
 
enum  CHIP_SSP_FRAME_FORMAT_T {
  SSP_FRAME_FORMAT_SPI = (0 << 4),
  SSP_FRAME_FORMAT_TI = (1u << 4),
  SSP_FRAME_FORMAT_MICROWIRE = (2u << 4)
}
 
enum  CHIP_SSP_BITS_T {
  SSP_BITS_4 = (3u << 0),
  SSP_BITS_5 = (4u << 0),
  SSP_BITS_6 = (5u << 0),
  SSP_BITS_7 = (6u << 0),
  SSP_BITS_8 = (7u << 0),
  SSP_BITS_9 = (8u << 0),
  SSP_BITS_10 = (9u << 0),
  SSP_BITS_11 = (10u << 0),
  SSP_BITS_12 = (11u << 0),
  SSP_BITS_13 = (12u << 0),
  SSP_BITS_14 = (13u << 0),
  SSP_BITS_15 = (14u << 0),
  SSP_BITS_16 = (15u << 0)
}
 
enum  CHIP_SSP_MODE_T {
  SSP_MODE_MASTER = (0 << 2),
  SSP_MODE_SLAVE = (1u << 2)
}
 

Functions

static void Chip_SSP_Enable (NSS_SSP_T *pSSP)
 
static void Chip_SSP_Disable (NSS_SSP_T *pSSP)
 
static void Chip_SSP_EnableLoopBack (NSS_SSP_T *pSSP)
 
static void Chip_SSP_DisableLoopBack (NSS_SSP_T *pSSP)
 
static SSP_INT_STATUS_T Chip_SSP_GetStatus (NSS_SSP_T *pSSP, SSP_STATUS_T Stat)
 
static uint32_t Chip_SSP_GetIntStatus (NSS_SSP_T *pSSP)
 
static SSP_INT_STATUS_T Chip_SSP_GetRawIntStatus (NSS_SSP_T *pSSP, SSP_RAWINTSTATUS_T RawInt)
 
static uint8_t Chip_SSP_GetDataSize (NSS_SSP_T *pSSP)
 
static void Chip_SSP_ClearIntPending (NSS_SSP_T *pSSP, SSP_INTCLEAR_T IntClear)
 
static void Chip_SSP_Int_Enable (NSS_SSP_T *pSSP)
 
static void Chip_SSP_Int_Disable (NSS_SSP_T *pSSP)
 
static uint16_t Chip_SSP_ReceiveFrame (NSS_SSP_T *pSSP)
 
static void Chip_SSP_SendFrame (NSS_SSP_T *pSSP, uint16_t tx_data)
 
void Chip_SSP_SetClockRate (NSS_SSP_T *pSSP, uint32_t clk_rate, uint32_t prescale)
 
static void Chip_SSP_SetFormat (NSS_SSP_T *pSSP, uint32_t bits, uint32_t frameFormat, uint32_t clockMode)
 
static void Chip_SSP_Set_Mode (NSS_SSP_T *pSSP, uint32_t mode)
 
void Chip_SSP_Int_FlushData (NSS_SSP_T *pSSP)
 
Status Chip_SSP_Int_RWFrames8Bits (NSS_SSP_T *pSSP, Chip_SSP_DATA_SETUP_T *xf_setup)
 
Status Chip_SSP_Int_RWFrames16Bits (NSS_SSP_T *pSSP, Chip_SSP_DATA_SETUP_T *xf_setup)
 
uint32_t Chip_SSP_RWFrames_Blocking (NSS_SSP_T *pSSP, Chip_SSP_DATA_SETUP_T *xf_setup)
 
uint32_t Chip_SSP_WriteFrames_Blocking (NSS_SSP_T *pSSP, uint8_t *buffer, uint32_t buffer_len)
 
uint32_t Chip_SSP_ReadFrames_Blocking (NSS_SSP_T *pSSP, uint8_t *buffer, uint32_t buffer_len)
 
void Chip_SSP_Init (NSS_SSP_T *pSSP)
 
void Chip_SSP_DeInit (NSS_SSP_T *pSSP)
 
void Chip_SSP_SetMaster (NSS_SSP_T *pSSP, bool master)
 
void Chip_SSP_SetBitRate (NSS_SSP_T *pSSP, uint32_t bitRate)
 
uint32_t Chip_SSP_GetBitRate (NSS_SSP_T *pSSP)
 

Data Structure Documentation

◆ NSS_SSP_T

struct NSS_SSP_T

SSP register block structure

Data Fields
__IO uint32_t CR0

Control Register 0. Selects the serial clock rate, bus type, and data size.

__IO uint32_t CR1

Control Register 1. Selects master/slave and other modes.

__IO uint32_t DR

Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO.

__I uint32_t SR

Status Register

__IO uint32_t CPSR

Clock Prescale Register

__IO uint32_t IMSC

Interrupt Mask Set and Clear Register

__I uint32_t RIS

Raw Interrupt Status Register

__I uint32_t MIS

Masked Interrupt Status Register

__O uint32_t ICR

SSPICR Interrupt Clear Register

◆ Chip_SSP_DATA_SETUP_T

struct Chip_SSP_DATA_SETUP_T

SSP data setup structure

Data Fields
void * tx_data

Pointer to transmit data

uint32_t tx_cnt

Transmit counter

void * rx_data

Pointer to transmit data

uint32_t rx_cnt

Receive counter

uint32_t length

Length of transfer data

Macro Definition Documentation

◆ SSP_CR0_DSS

#define SSP_CR0_DSS (   n)    ((uint32_t) ((n) & 0xF))

SSP data size select, must be 4 bits to 16 bits

◆ SSP_CR0_FRF_SPI

#define SSP_CR0_FRF_SPI   ((uint32_t) (0 << 4))

SSP control 0 Motorola SPI mode

◆ SSP_CR0_FRF_TI

#define SSP_CR0_FRF_TI   ((uint32_t) (1 << 4))

SSP control 0 TI synchronous serial mode

◆ SSP_CR0_FRF_MICROWIRE

#define SSP_CR0_FRF_MICROWIRE   ((uint32_t) (2 << 4))

SSP control 0 National Micro-wire mode

◆ SSP_CR0_CPOL_LO

#define SSP_CR0_CPOL_LO   ((uint32_t) (0))

SPI clock polarity bit Low (used in SPI mode only), maintains the bus clock low between frames

◆ SSP_CR0_CPOL_HI

#define SSP_CR0_CPOL_HI   ((uint32_t) (1 << 6))

SPI clock polarity bit High (used in SPI mode only), maintains the bus clock high between frames

◆ SSP_CR0_CPHA_FIRST

#define SSP_CR0_CPHA_FIRST   ((uint32_t) (0))

SPI clock out phase bit FIRST(used in SPI mode only), captures data on the first clock transition of the frame

◆ SSP_CR0_CPHA_SECOND

#define SSP_CR0_CPHA_SECOND   ((uint32_t) (1 << 7))

SPI clock out phase bit SECOND (used in SPI mode only), captures data on the second clock transition of the frame

◆ SSP_CR0_SCR

#define SSP_CR0_SCR (   n)    ((uint32_t) ((n & 0xFF) << 8))

SSP serial clock rate value load macro, divider rate is PERIPH_CLK / (cpsr * (SCR + 1))

◆ SSP_CR0_BITMASK

#define SSP_CR0_BITMASK   ((uint32_t) (0xFFFF))

SSP CR0 bit mask

◆ SSP_CR1_LBM_EN

#define SSP_CR1_LBM_EN   ((uint32_t) (1 << 0))

SSP control 1 loopback mode enable bit

◆ SSP_CR1_SSP_EN

#define SSP_CR1_SSP_EN   ((uint32_t) (1 << 1))

SSP control 1 enable bit

◆ SSP_CR1_SLAVE_EN

#define SSP_CR1_SLAVE_EN   ((uint32_t) (1 << 2))

SSP control 1 slave enable

◆ SSP_CR1_MASTER_EN

#define SSP_CR1_MASTER_EN   ((uint32_t) (0))

SSP control 1 master enable

◆ SSP_CR1_SO_DISABLE

#define SSP_CR1_SO_DISABLE   ((uint32_t) (1 << 3))

SSP control 1 slave out disable bit, disables transmit line in slave mode

◆ SSP_CR1_BITMASK

#define SSP_CR1_BITMASK   ((uint32_t) (0x0F))

SSP CR1 bit mask

◆ SSP_CPSR_BITMASK

#define SSP_CPSR_BITMASK   ((uint32_t) (0xFF))

SSP CPSR bit mask

◆ SSP_DR_BITMASK

#define SSP_DR_BITMASK (   n)    ((n) & 0xFFFF)

SSP data bit mask

◆ SSP_SR_BITMASK

#define SSP_SR_BITMASK   ((uint32_t) (0x1F))

SSP SR bit mask

◆ SSP_ICR_BITMASK

#define SSP_ICR_BITMASK   ((uint32_t) (0x03))

ICR bit mask

Enumeration Type Documentation

◆ SSP_INT_STATUS_T

Flag Status and Interrupt Flag Status type definition

Enumerator
RESET 

Reset status

SET 

Set status

◆ Status

enum Status

Error status type definition

Enumerator
ERROR 

Error

SUCCESS 

Success

◆ SSP_STATUS_T

SSP Type for Status

Enumerator
SSP_STAT_TFE 

TX FIFO Empty

SSP_STAT_TNF 

TX FIFO not full

SSP_STAT_RNE 

RX FIFO not empty

SSP_STAT_RFF 

RX FIFO full

SSP_STAT_BSY 

SSP Busy

◆ SSP_INTMASK_T

SSP Type for Interrupt Mask

Enumerator
SSP_RORIM 

Overrun

SSP_RTIM 

TimeOut

SSP_RXIM 

Rx FIFO is at least half full

SSP_TXIM 

Tx FIFO is at least half empty

SSP_INT_MASK_BITMASK 

All select Mask

◆ SSP_MASKINTSTATUS_T

SSP Type for Masked Interrupt Status

Enumerator
SSP_RORMIS 

Overrun

SSP_RTMIS 

TimeOut

SSP_RXMIS 

Rx FIFO is at least half full

SSP_TXMIS 

Tx FIFO is at least half empty

SSP_MASK_INT_STAT_BITMASK 

All select Mask

◆ SSP_RAWINTSTATUS_T

SSP Type for Raw Interrupt Status

Enumerator
SSP_RORRIS 

Overrun

SSP_RTRIS 

TimeOut

SSP_RXRIS 

Rx FIFO is at least half full

SSP_TXRIS 

Tx FIFO is at least half empty

SSP_RAW_INT_STAT_BITMASK 

All select Mask

◆ SSP_INTCLEAR_T

SSP Interrupt clear masks

Enumerator
SSP_RORIC 

Overrun Mask

SSP_RTIC 

TimeOut Mask

SSP_INT_CLEAR_BITMASK 

Clear all Mask

◆ CHIP_SSP_CLOCK_MODE_T

SSP clock format

Enumerator
SSP_CLOCK_CPHA0_CPOL0 

CPHA = 0, CPOL = 0

SSP_CLOCK_CPHA0_CPOL1 

CPHA = 0, CPOL = 1

SSP_CLOCK_CPHA1_CPOL0 

CPHA = 1, CPOL = 0

SSP_CLOCK_CPHA1_CPOL1 

CPHA = 1, CPOL = 1

SSP_CLOCK_MODE0 

alias for SSP_CLOCK_CPHA0_CPOL0

SSP_CLOCK_MODE1 

alias for SSP_CLOCK_CPHA1_CPOL0

SSP_CLOCK_MODE2 

alias for SSP_CLOCK_CPHA0_CPOL1

SSP_CLOCK_MODE3 

alias for SSP_CLOCK_CPHA1_CPOL1

◆ CHIP_SSP_FRAME_FORMAT_T

SSP frame format

Enumerator
SSP_FRAME_FORMAT_SPI 

Frame format: SPI

SSP_FRAME_FORMAT_TI 

Frame format: TI SSI

SSP_FRAME_FORMAT_MICROWIRE 

Frame format: Microwire

◆ CHIP_SSP_BITS_T

Number of bits per frame

Enumerator
SSP_BITS_4 

4 bits/frame

SSP_BITS_5 

5 bits/frame

SSP_BITS_6 

6 bits/frame

SSP_BITS_7 

7 bits/frame

SSP_BITS_8 

8 bits/frame

SSP_BITS_9 

9 bits/frame

SSP_BITS_10 

10 bits/frame

SSP_BITS_11 

11 bits/frame

SSP_BITS_12 

12 bits/frame

SSP_BITS_13 

13 bits/frame

SSP_BITS_14 

14 bits/frame

SSP_BITS_15 

15 bits/frame

SSP_BITS_16 

16 bits/frame

◆ CHIP_SSP_MODE_T

SSP mode

Enumerator
SSP_MODE_MASTER 

Master mode

SSP_MODE_SLAVE 

Slave mode

Function Documentation

◆ Chip_SSP_Enable()

static void Chip_SSP_Enable ( NSS_SSP_T pSSP)
inlinestatic

Enable SSP operation

Parameters
pSSP: The base address of the SSP peripheral on the chip

< SSP control 1 enable bit

◆ Chip_SSP_Disable()

static void Chip_SSP_Disable ( NSS_SSP_T pSSP)
inlinestatic

Disable SSP operation

Parameters
pSSP: The base address of the SSP peripheral on the chip

< SSP control 1 enable bit
< SSP CR1 bit mask

◆ Chip_SSP_EnableLoopBack()

static void Chip_SSP_EnableLoopBack ( NSS_SSP_T pSSP)
inlinestatic

Enable loopback mode

Parameters
pSSP: The base address of the SSP peripheral on the chip
Note
In loopback mode, serial input is taken from the serial output (MOSI or MISO) rather than the serial input pin.

< SSP control 1 loopback mode enable bit

◆ Chip_SSP_DisableLoopBack()

static void Chip_SSP_DisableLoopBack ( NSS_SSP_T pSSP)
inlinestatic

Disable loopback mode

Parameters
pSSP: The base address of the SSP peripheral on the chip
Note
In loopback mode, serial input is taken from the serial output (MOSI or MISO) rather than the serial input pin.

< SSP control 1 loopback mode enable bit
< SSP CR1 bit mask

◆ Chip_SSP_GetStatus()

static SSP_INT_STATUS_T Chip_SSP_GetStatus ( NSS_SSP_T pSSP,
SSP_STATUS_T  Stat 
)
inlinestatic

Get the current status of SSP controller

Parameters
pSSP: The base address of the SSP peripheral on the chip
Stat: Type of status, as given below :
Returns
SSP controller status, SET or RESET

◆ Chip_SSP_GetIntStatus()

static uint32_t Chip_SSP_GetIntStatus ( NSS_SSP_T pSSP)
inlinestatic

Get the masked interrupt status

Parameters
pSSP: The base address of the SSP peripheral on the chip
Returns
SSP Masked Interrupt Status Register value
Note
The return value contains a 1 for each interrupt condition that is asserted and enabled (masked)

◆ Chip_SSP_GetRawIntStatus()

static SSP_INT_STATUS_T Chip_SSP_GetRawIntStatus ( NSS_SSP_T pSSP,
SSP_RAWINTSTATUS_T  RawInt 
)
inlinestatic

Get the raw interrupt status

Parameters
pSSP: The base address of the SSP peripheral on the chip
RawInt: Interrupt condition to get status for, as given below :
Returns
Raw interrupt status corresponding to the requested interrupt condition, SET or RESET
Note
Get the status of each interrupt condition, regardless of whether or not the interrupt is enabled

◆ Chip_SSP_GetDataSize()

static uint8_t Chip_SSP_GetDataSize ( NSS_SSP_T pSSP)
inlinestatic

Get the number of bits transferred in each frame

Parameters
pSSP: The base address of the SSP peripheral on the chip
Returns
the number of bits transferred in each frame minus one
Note
The return value is 0x03 -> 0xF corresponding to 4bit -> 16bit transfer

< SSP data size select, must be 4 bits to 16 bits

◆ Chip_SSP_ClearIntPending()

static void Chip_SSP_ClearIntPending ( NSS_SSP_T pSSP,
SSP_INTCLEAR_T  IntClear 
)
inlinestatic

Clear the corresponding interrupt condition(s) in the SSP controller

Parameters
pSSP: The base address of the SSP peripheral on the chip
IntClear: Type of cleared interrupt, as given below :
Note
Software can clear one or more interrupt condition(s) in the SSP controller

◆ Chip_SSP_Int_Enable()

static void Chip_SSP_Int_Enable ( NSS_SSP_T pSSP)
inlinestatic

Enable interrupt for the SSP

Parameters
pSSP: The base address of the SSP peripheral on the chip
Note
The implementation supports the interrupt type "Tx FIFO is at least half empty" only

◆ Chip_SSP_Int_Disable()

static void Chip_SSP_Int_Disable ( NSS_SSP_T pSSP)
inlinestatic

Disable interrupt for the SSP

Parameters
pSSP: The base address of the SSP peripheral on the chip
Note
The implementation supports the interrupt type "Tx FIFO is at least half empty" only

◆ Chip_SSP_ReceiveFrame()

static uint16_t Chip_SSP_ReceiveFrame ( NSS_SSP_T pSSP)
inlinestatic

Get received 16-bit SSP data

Parameters
pSSP: The base address of the SSP peripheral on the chip
Returns
SSP 16-bit data received

< SSP data bit mask

◆ Chip_SSP_SendFrame()

static void Chip_SSP_SendFrame ( NSS_SSP_T pSSP,
uint16_t  tx_data 
)
inlinestatic

Send SSP 16-bit data

Parameters
pSSP: The base address of the SSP peripheral on the chip
tx_data: SSP 16-bit data to be transmitted

< SSP data bit mask

◆ Chip_SSP_SetClockRate()

void Chip_SSP_SetClockRate ( NSS_SSP_T pSSP,
uint32_t  clk_rate,
uint32_t  prescale 
)

Set up output clocks per bit for SSP bus

Parameters
pSSP: The base address of the SSP peripheral on the chip
clk_ratefs: The number of prescaler-output clocks per bit on the bus, minus one
prescale: The factor by which the Prescaler divides the SSP peripheral clock PCLK
Note
The bit frequency is PCLK / (prescale x[clk_rate+1])

◆ Chip_SSP_SetFormat()

static void Chip_SSP_SetFormat ( NSS_SSP_T pSSP,
uint32_t  bits,
uint32_t  frameFormat,
uint32_t  clockMode 
)
inlinestatic

Set up the SSP frame format

Parameters
pSSP: The base address of the SSP peripheral on the chip
bits: The number of bits transferred in each frame, should be between SSP_BITS_4 and SSP_BITS_16
frameFormat: Frame format, as given below :
clockMode: Select Clock polarity and Clock phase, as given below :
Note
The clockFormat is only used in SPI mode

◆ Chip_SSP_Set_Mode()

static void Chip_SSP_Set_Mode ( NSS_SSP_T pSSP,
uint32_t  mode 
)
inlinestatic

Set the SSP working as master or slave mode

Parameters
pSSP: The base address of the SSP peripheral on the chip
mode: Operating mode, as given below:

◆ Chip_SSP_Int_FlushData()

void Chip_SSP_Int_FlushData ( NSS_SSP_T pSSP)

Clean all data in RX FIFO of SSP

Parameters
pSSP: The base address of the SSP peripheral on the chip

◆ Chip_SSP_Int_RWFrames8Bits()

Status Chip_SSP_Int_RWFrames8Bits ( NSS_SSP_T pSSP,
Chip_SSP_DATA_SETUP_T xf_setup 
)

SSP Interrupt Read/Write with 8-bit frame width

Parameters
pSSP: The base address of the SSP peripheral on the chip
xf_setup: Pointer to a SSP_DATA_SETUP_T structure that contains specified information about transmit/receive data configuration
Returns
SUCCESS or ERROR

◆ Chip_SSP_Int_RWFrames16Bits()

Status Chip_SSP_Int_RWFrames16Bits ( NSS_SSP_T pSSP,
Chip_SSP_DATA_SETUP_T xf_setup 
)

SSP Interrupt Read/Write with 16-bit frame width

Parameters
pSSP: The base address of the SSP peripheral on the chip
xf_setup: Pointer to a SSP_DATA_SETUP_T structure that contains specified information about transmit/receive data configuration
Returns
SUCCESS or ERROR

◆ Chip_SSP_RWFrames_Blocking()

uint32_t Chip_SSP_RWFrames_Blocking ( NSS_SSP_T pSSP,
Chip_SSP_DATA_SETUP_T xf_setup 
)

SSP Polling Read/Write in blocking mode

Parameters
pSSP: The base address of the SSP peripheral on the chip
xf_setup: Pointer to a SSP_DATA_SETUP_T structure that contains specified information about transmit/receive data configuration
Returns
Actual data transfer length
Note
This function can be used in both master and slave mode. It starts with a writing phase and after that, a reading phase is generated to read any data available in RX_FIFO. All needed information is prepared through xf_setup param.

◆ Chip_SSP_WriteFrames_Blocking()

uint32_t Chip_SSP_WriteFrames_Blocking ( NSS_SSP_T pSSP,
uint8_t *  buffer,
uint32_t  buffer_len 
)

SSP Polling Write in blocking mode

Parameters
pSSP: The base address of the SSP peripheral on the chip
buffer: Buffer address
buffer_len: Buffer length
Returns
Actual data transfer length
Note
This function can be used in both master and slave mode. First, a writing operation will send the needed data. After that, a dummy reading operation is generated to clear data buffer

◆ Chip_SSP_ReadFrames_Blocking()

uint32_t Chip_SSP_ReadFrames_Blocking ( NSS_SSP_T pSSP,
uint8_t *  buffer,
uint32_t  buffer_len 
)

SSP Polling Read in blocking mode

Parameters
pSSP: The base address of the SSP peripheral on the chip
buffer: Buffer address
buffer_len: The length of buffer
Returns
Actual data transfer length
Note
This function can be used in both master and slave mode. First, a dummy writing operation is generated to clear data buffer. After that, a reading operation will receive the needed data

◆ Chip_SSP_Init()

void Chip_SSP_Init ( NSS_SSP_T pSSP)

Initialize the SSP

Parameters
pSSP: The base address of the SSP peripheral on the chip

◆ Chip_SSP_DeInit()

void Chip_SSP_DeInit ( NSS_SSP_T pSSP)

De-initialise the SSP

Parameters
pSSP: The base address of the SSP peripheral on the chip
Note
The SSP controller is disabled

◆ Chip_SSP_SetMaster()

void Chip_SSP_SetMaster ( NSS_SSP_T pSSP,
bool  master 
)

Set the SSP operating modes, master or slave

Parameters
pSSP: The base address of the SSP peripheral on the chip
master: 1 to set master, 0 to set slave

◆ Chip_SSP_SetBitRate()

void Chip_SSP_SetBitRate ( NSS_SSP_T pSSP,
uint32_t  bitRate 
)

Set the clock frequency for SSP interface

Parameters
pSSP: The base address of the SSP peripheral on the chip
bitRate: The SSP bit rate in bits per seconds
Note
Please refer to SSP Clock rates for more information on SSP clock and bitrate

◆ Chip_SSP_GetBitRate()

uint32_t Chip_SSP_GetBitRate ( NSS_SSP_T pSSP)

Get the clock frequency for SSP interface

Parameters
pSSP: The base address of the SSP peripheral on the chip
Returns
The SSP bit rate in bits per second
Note
Please refer to SSP Clock rates for more information on SSP clock and bitrate