NHS31xx SW API
core_cmFunc.h
1 /**************************************************************************/
24 #ifndef __CORE_CMFUNC_H
25 #define __CORE_CMFUNC_H
26 
27 
28 /* ########################### Core Function Access ########################### */
34 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
35 /* ARM armcc specific functions */
36 
37 #if (__ARMCC_VERSION < 400677)
38  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
39 #endif
40 
41 /* intrinsic void __enable_irq(); */
42 /* intrinsic void __disable_irq(); */
43 
50 __STATIC_INLINE uint32_t __get_CONTROL(void)
51 {
52  register uint32_t __regControl __ASM("control");
53  return(__regControl);
54 }
55 
56 
63 __STATIC_INLINE void __set_CONTROL(uint32_t control)
64 {
65  register uint32_t __regControl __ASM("control");
66  __regControl = control;
67 }
68 
69 
76 __STATIC_INLINE uint32_t __get_IPSR(void)
77 {
78  register uint32_t __regIPSR __ASM("ipsr");
79  return(__regIPSR);
80 }
81 
82 
89 __STATIC_INLINE uint32_t __get_APSR(void)
90 {
91  register uint32_t __regAPSR __ASM("apsr");
92  return(__regAPSR);
93 }
94 
95 
102 __STATIC_INLINE uint32_t __get_xPSR(void)
103 {
104  register uint32_t __regXPSR __ASM("xpsr");
105  return(__regXPSR);
106 }
107 
108 
115 __STATIC_INLINE uint32_t __get_PSP(void)
116 {
117  register uint32_t __regProcessStackPointer __ASM("psp");
118  return(__regProcessStackPointer);
119 }
120 
121 
128 __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
129 {
130  register uint32_t __regProcessStackPointer __ASM("psp");
131  __regProcessStackPointer = topOfProcStack;
132 }
133 
134 
141 __STATIC_INLINE uint32_t __get_MSP(void)
142 {
143  register uint32_t __regMainStackPointer __ASM("msp");
144  return(__regMainStackPointer);
145 }
146 
147 
154 __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
155 {
156  register uint32_t __regMainStackPointer __ASM("msp");
157  __regMainStackPointer = topOfMainStack;
158 }
159 
160 
167 __STATIC_INLINE uint32_t __get_PRIMASK(void)
168 {
169  register uint32_t __regPriMask __ASM("primask");
170  return(__regPriMask);
171 }
172 
173 
180 __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
181 {
182  register uint32_t __regPriMask __ASM("primask");
183  __regPriMask = (priMask);
184 }
185 
186 
187 #if (__CORTEX_M >= 0x03)
188 
194 #define __enable_fault_irq __enable_fiq
195 
196 
202 #define __disable_fault_irq __disable_fiq
203 
204 
211 __STATIC_INLINE uint32_t __get_BASEPRI(void)
212 {
213  register uint32_t __regBasePri __ASM("basepri");
214  return(__regBasePri);
215 }
216 
217 
224 __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
225 {
226  register uint32_t __regBasePri __ASM("basepri");
227  __regBasePri = (basePri & 0xff);
228 }
229 
230 
237 __STATIC_INLINE uint32_t __get_FAULTMASK(void)
238 {
239  register uint32_t __regFaultMask __ASM("faultmask");
240  return(__regFaultMask);
241 }
242 
243 
250 __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
251 {
252  register uint32_t __regFaultMask __ASM("faultmask");
253  __regFaultMask = (faultMask & (uint32_t)1);
254 }
255 
256 #endif /* (__CORTEX_M >= 0x03) */
257 
258 
259 #if (__CORTEX_M == 0x04)
260 
267 __STATIC_INLINE uint32_t __get_FPSCR(void)
268 {
269 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
270  register uint32_t __regfpscr __ASM("fpscr");
271  return(__regfpscr);
272 #else
273  return(0);
274 #endif
275 }
276 
277 
284 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
285 {
286 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
287  register uint32_t __regfpscr __ASM("fpscr");
288  __regfpscr = (fpscr);
289 #endif
290 }
291 
292 #endif /* (__CORTEX_M == 0x04) */
293 
294 
295 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
296 /* IAR iccarm specific functions */
297 
298 #include <cmsis_iar.h>
299 
300 
301 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
302 /* TI CCS specific functions */
303 
304 #include <cmsis_ccs.h>
305 
306 
307 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
308 /* GNU gcc specific functions */
309 
315 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
316 {
317  __ASM volatile ("cpsie i");
318 }
319 
320 
326 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
327 {
328  __ASM volatile ("cpsid i");
329 }
330 
331 
338 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
339 {
340  uint32_t result;
341 
342  __ASM volatile ("MRS %0, control" : "=r" (result) );
343  return(result);
344 }
345 
346 
353 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
354 {
355  __ASM volatile ("MSR control, %0" : : "r" (control) );
356 }
357 
358 
365 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
366 {
367  uint32_t result;
368 
369  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
370  return(result);
371 }
372 
373 
380 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
381 {
382  uint32_t result;
383 
384  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
385  return(result);
386 }
387 
388 
395 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
396 {
397  uint32_t result;
398 
399  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
400  return(result);
401 }
402 
403 
410 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
411 {
412  register uint32_t result;
413 
414  __ASM volatile ("MRS %0, psp\n" : "=r" (result) );
415  return(result);
416 }
417 
418 
425 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
426 {
427  __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) );
428 }
429 
430 
437 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
438 {
439  register uint32_t result;
440 
441  __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
442  return(result);
443 }
444 
445 
452 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
453 {
454  __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) );
455 }
456 
457 
464 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
465 {
466  uint32_t result;
467 
468  __ASM volatile ("MRS %0, primask" : "=r" (result) );
469  return(result);
470 }
471 
472 
479 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
480 {
481  __ASM volatile ("MSR primask, %0" : : "r" (priMask) );
482 }
483 
484 
485 #if (__CORTEX_M >= 0x03)
486 
492 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
493 {
494  __ASM volatile ("cpsie f");
495 }
496 
497 
503 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
504 {
505  __ASM volatile ("cpsid f");
506 }
507 
508 
515 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
516 {
517  uint32_t result;
518 
519  __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
520  return(result);
521 }
522 
523 
530 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
531 {
532  __ASM volatile ("MSR basepri, %0" : : "r" (value) );
533 }
534 
535 
542 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
543 {
544  uint32_t result;
545 
546  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
547  return(result);
548 }
549 
550 
557 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
558 {
559  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
560 }
561 
562 #endif /* (__CORTEX_M >= 0x03) */
563 
564 
565 #if (__CORTEX_M == 0x04)
566 
573 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
574 {
575 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
576  uint32_t result;
577 
578  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
579  return(result);
580 #else
581  return(0);
582 #endif
583 }
584 
585 
592 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
593 {
594 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
595  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) );
596 #endif
597 }
598 
599 #endif /* (__CORTEX_M == 0x04) */
600 
601 
602 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
603 /* TASKING carm specific functions */
604 
605 /*
606  * The CMSIS functions have been implemented as intrinsics in the compiler.
607  * Please use "carm -?i" to get an up to date list of all instrinsics,
608  * Including the CMSIS ones.
609  */
610 
611 #endif
612 
616 #endif /* __CORE_CMFUNC_H */
#define __STATIC_INLINE
Definition: core_cm0plus.h:78
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
Set Priority Mask.
Definition: core_cmFunc.h:479
__STATIC_INLINE uint32_t __get_PSP(void)
Get Process Stack Pointer.
Definition: core_cmFunc.h:410
__STATIC_INLINE uint32_t __get_CONTROL(void)
Get Control Register.
Definition: core_cmFunc.h:338
__STATIC_INLINE uint32_t __get_IPSR(void)
Get IPSR Register.
Definition: core_cmFunc.h:365
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
Set Process Stack Pointer.
Definition: core_cmFunc.h:425
#define __ASM
Definition: core_cm0plus.h:76
__STATIC_INLINE uint32_t __get_PRIMASK(void)
Get Priority Mask.
Definition: core_cmFunc.h:464
__STATIC_INLINE void __enable_irq(void)
Enable IRQ Interrupts.
Definition: core_cmFunc.h:315
__STATIC_INLINE uint32_t __get_MSP(void)
Get Main Stack Pointer.
Definition: core_cmFunc.h:437
__STATIC_INLINE uint32_t __get_xPSR(void)
Get xPSR Register.
Definition: core_cmFunc.h:395
__STATIC_INLINE uint32_t __get_APSR(void)
Get APSR Register.
Definition: core_cmFunc.h:380
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
Set Main Stack Pointer.
Definition: core_cmFunc.h:452
__STATIC_INLINE void __set_CONTROL(uint32_t control)
Set Control Register.
Definition: core_cmFunc.h:353
__STATIC_INLINE void __disable_irq(void)
Disable IRQ Interrupts.
Definition: core_cmFunc.h:326