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NHS31xx SW API
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Provides an access layer to the functionality of the Cortex-M0+ core.
Please refer to Functions and Instructions Reference for all the available functions and to CMSIS Core Instruction Interface for all the available instructions.
Modules | |
CMSIS CM0+ definitions | |
CMSIS Core Instruction Interface | |
Defines and Type Definitions | |
Functions and Instructions Reference | |
Macros | |
#define | __CM0_REV 0x0000 |
#define | __MPU_PRESENT 0 |
#define | __NVIC_PRIO_BITS 2 |
#define | __Vendor_SysTickConfig 0 |
Enumerations | |
enum | IRQn_Type { Reset_IRQn = -15, NonMaskableInt_IRQn = -14, HardFault_IRQn = -13, SVCall_IRQn = -5, PendSV_IRQn = -2, SysTick_IRQn = -1, PIO0_0_IRQn = 0, PIO0_1_IRQn = 1, PIO0_2_IRQn = 2, PIO0_3_IRQn = 3, PIO0_4_IRQn = 4, PIO0_5_IRQn = 5, PIO0_6_IRQn = 6, PIO0_7_IRQn = 7, PIO0_8_IRQn = 8, PIO0_9_IRQn = 9, PIO0_10_IRQn = 10, RFFIELD_IRQn = 11, RTCPWREQ_IRQn = 12, NFC_IRQn = 13, RTC_IRQn = 14, I2C0_IRQn = 15, CT16B0_IRQn = 16, PMUFLD_IRQn = 17, CT32B0_IRQn = 18, PMUBOD_IRQn = 19, SSP0_IRQn = 20, TSEN_IRQn = 21, C2D_IRQn = 22, Reserved1_IRQn = 23, I2D_IRQn = 24, ADCDAC_IRQn = 25, WDT_IRQn = 26, FLASH_IRQn = 27, EEPROM_IRQn = 28, Reserved2_IRQn = 29, Reserved3_IRQn = 30, PIO0_IRQn = 31 } |
#define __CM0_REV 0x0000 |
Cortex-M0 Core Revision
#define __MPU_PRESENT 0 |
MPU present or not
#define __NVIC_PRIO_BITS 2 |
Number of Bits used for Priority Levels
#define __Vendor_SysTickConfig 0 |
Set to 1 if different SysTick Config is used
enum IRQn_Type |
Defines the supported NVIC Peripheral interrupts