NHS31xx SW API

Detailed Description

Data Structures

struct  SCB_Type
 

Macros

#define SCB_CPUID_IMPLEMENTER_Pos   24
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_VARIANT_Pos   20
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Pos   16
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_PARTNO_Pos   4
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_REVISION_Pos   0
 
#define SCB_CPUID_REVISION_Msk   (0xFUL << SCB_CPUID_REVISION_Pos)
 
#define SCB_ICSR_NMIPENDSET_Pos   31
 
#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)
 
#define SCB_ICSR_PENDSVSET_Pos   28
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVCLR_Pos   27
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSTSET_Pos   26
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTCLR_Pos   25
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Pos   23
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPENDING_Pos   22
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Pos   12
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_VECTACTIVE_Pos   0
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)
 
#define SCB_AIRCR_VECTKEY_Pos   16
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_ENDIANESS_Pos   15
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_SCR_SEVONPEND_Pos   4
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SLEEPDEEP_Pos   2
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Pos   1
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_CCR_STKALIGN_Pos   9
 
#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Pos   3
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 

Data Structure Documentation

◆ SCB_Type

struct SCB_Type
Data Fields
volatile const uint32_t CPUID

< Defines 'read only' permissions Offset: 0x000 (R/ ) CPUID Base Register

volatile uint32_t ICSR

< Defines 'read / write' permissions Offset: 0x004 (R/W) Interrupt Control and State Register

uint32_t RESERVED0
volatile uint32_t AIRCR

< Defines 'read / write' permissions Offset: 0x00C (R/W) Application Interrupt and Reset Control Register

volatile uint32_t SCR

< Defines 'read / write' permissions Offset: 0x010 (R/W) System Control Register

volatile uint32_t CCR

< Defines 'read / write' permissions Offset: 0x014 (R/W) Configuration Control Register

uint32_t RESERVED1
volatile uint32_t SHP[2]

< Defines 'read / write' permissions Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED

volatile uint32_t SHCSR

< Defines 'read / write' permissions Offset: 0x024 (R/W) System Handler Control and State Register

Macro Definition Documentation

◆ SCB_CPUID_IMPLEMENTER_Pos

#define SCB_CPUID_IMPLEMENTER_Pos   24

SCB CPUID: IMPLEMENTER Position

◆ SCB_CPUID_IMPLEMENTER_Msk

#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

◆ SCB_CPUID_VARIANT_Pos

#define SCB_CPUID_VARIANT_Pos   20

SCB CPUID: VARIANT Position

◆ SCB_CPUID_VARIANT_Msk

#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

◆ SCB_CPUID_ARCHITECTURE_Pos

#define SCB_CPUID_ARCHITECTURE_Pos   16

SCB CPUID: ARCHITECTURE Position

◆ SCB_CPUID_ARCHITECTURE_Msk

#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

◆ SCB_CPUID_PARTNO_Pos

#define SCB_CPUID_PARTNO_Pos   4

SCB CPUID: PARTNO Position

◆ SCB_CPUID_PARTNO_Msk

#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

◆ SCB_CPUID_REVISION_Pos

#define SCB_CPUID_REVISION_Pos   0

SCB CPUID: REVISION Position

◆ SCB_CPUID_REVISION_Msk

#define SCB_CPUID_REVISION_Msk   (0xFUL << SCB_CPUID_REVISION_Pos)

SCB CPUID: REVISION Mask

◆ SCB_ICSR_NMIPENDSET_Pos

#define SCB_ICSR_NMIPENDSET_Pos   31

SCB ICSR: NMIPENDSET Position

◆ SCB_ICSR_NMIPENDSET_Msk

#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)

SCB ICSR: NMIPENDSET Mask

◆ SCB_ICSR_PENDSVSET_Pos

#define SCB_ICSR_PENDSVSET_Pos   28

SCB ICSR: PENDSVSET Position

◆ SCB_ICSR_PENDSVSET_Msk

#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

◆ SCB_ICSR_PENDSVCLR_Pos

#define SCB_ICSR_PENDSVCLR_Pos   27

SCB ICSR: PENDSVCLR Position

◆ SCB_ICSR_PENDSVCLR_Msk

#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

◆ SCB_ICSR_PENDSTSET_Pos

#define SCB_ICSR_PENDSTSET_Pos   26

SCB ICSR: PENDSTSET Position

◆ SCB_ICSR_PENDSTSET_Msk

#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

◆ SCB_ICSR_PENDSTCLR_Pos

#define SCB_ICSR_PENDSTCLR_Pos   25

SCB ICSR: PENDSTCLR Position

◆ SCB_ICSR_PENDSTCLR_Msk

#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

◆ SCB_ICSR_ISRPREEMPT_Pos

#define SCB_ICSR_ISRPREEMPT_Pos   23

SCB ICSR: ISRPREEMPT Position

◆ SCB_ICSR_ISRPREEMPT_Msk

#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

◆ SCB_ICSR_ISRPENDING_Pos

#define SCB_ICSR_ISRPENDING_Pos   22

SCB ICSR: ISRPENDING Position

◆ SCB_ICSR_ISRPENDING_Msk

#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

◆ SCB_ICSR_VECTPENDING_Pos

#define SCB_ICSR_VECTPENDING_Pos   12

SCB ICSR: VECTPENDING Position

◆ SCB_ICSR_VECTPENDING_Msk

#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

◆ SCB_ICSR_VECTACTIVE_Pos

#define SCB_ICSR_VECTACTIVE_Pos   0

SCB ICSR: VECTACTIVE Position

◆ SCB_ICSR_VECTACTIVE_Msk

#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)

SCB ICSR: VECTACTIVE Mask

◆ SCB_AIRCR_VECTKEY_Pos

#define SCB_AIRCR_VECTKEY_Pos   16

SCB AIRCR: VECTKEY Position

◆ SCB_AIRCR_VECTKEY_Msk

#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

◆ SCB_AIRCR_VECTKEYSTAT_Pos

#define SCB_AIRCR_VECTKEYSTAT_Pos   16

SCB AIRCR: VECTKEYSTAT Position

◆ SCB_AIRCR_VECTKEYSTAT_Msk

#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

◆ SCB_AIRCR_ENDIANESS_Pos

#define SCB_AIRCR_ENDIANESS_Pos   15

SCB AIRCR: ENDIANESS Position

◆ SCB_AIRCR_ENDIANESS_Msk

#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

◆ SCB_AIRCR_SYSRESETREQ_Pos

#define SCB_AIRCR_SYSRESETREQ_Pos   2

SCB AIRCR: SYSRESETREQ Position

◆ SCB_AIRCR_SYSRESETREQ_Msk

#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

◆ SCB_AIRCR_VECTCLRACTIVE_Pos

#define SCB_AIRCR_VECTCLRACTIVE_Pos   1

SCB AIRCR: VECTCLRACTIVE Position

◆ SCB_AIRCR_VECTCLRACTIVE_Msk

#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

◆ SCB_SCR_SEVONPEND_Pos

#define SCB_SCR_SEVONPEND_Pos   4

SCB SCR: SEVONPEND Position

◆ SCB_SCR_SEVONPEND_Msk

#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

◆ SCB_SCR_SLEEPDEEP_Pos

#define SCB_SCR_SLEEPDEEP_Pos   2

SCB SCR: SLEEPDEEP Position

◆ SCB_SCR_SLEEPDEEP_Msk

#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

◆ SCB_SCR_SLEEPONEXIT_Pos

#define SCB_SCR_SLEEPONEXIT_Pos   1

SCB SCR: SLEEPONEXIT Position

◆ SCB_SCR_SLEEPONEXIT_Msk

#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

◆ SCB_CCR_STKALIGN_Pos

#define SCB_CCR_STKALIGN_Pos   9

SCB CCR: STKALIGN Position

◆ SCB_CCR_STKALIGN_Msk

#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)

SCB CCR: STKALIGN Mask

◆ SCB_CCR_UNALIGN_TRP_Pos

#define SCB_CCR_UNALIGN_TRP_Pos   3

SCB CCR: UNALIGN_TRP Position

◆ SCB_CCR_UNALIGN_TRP_Msk

#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

◆ SCB_SHCSR_SVCALLPENDED_Pos

#define SCB_SHCSR_SVCALLPENDED_Pos   15

SCB SHCSR: SVCALLPENDED Position

◆ SCB_SHCSR_SVCALLPENDED_Msk

#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask