NHS31xx SW API
chip: Peripheral addresses and register set declarations

Detailed Description

Aggregates the addresses and handle definitions for all the peripherals of the IC.

Data Structures

struct  NFC_UID_T
 

Macros

#define ASSERT(expr)   /* Prevent a compiler warning for unused variables */
 
#define SDK_VERSION   12_4_nhs3100
 
#define NSS_SFRO_FREQUENCY   8000000
 
#define NSS_TFRO_FREQUENCY   32768
 
#define EEPROM_START   0x30000000
 
#define EEPROM_ROW_SIZE   64
 
#define EEPROM_NR_OF_R_ROWS   64
 
#define EEPROM_NR_OF_RW_ROWS   58
 
#define FLASH_START   0
 
#define FLASH_SECTOR_SIZE   1024
 
#define FLASH_PAGE_SIZE   64
 
#define FLASH_PAGES_PER_SECTOR   (FLASH_SECTOR_SIZE / FLASH_PAGE_SIZE)
 
#define FLASH_NR_OF_R_SECTORS   32
 
#define FLASH_NR_OF_RW_SECTORS   30
 
#define NSS_NFC_UID_BASE   (EEPROM_START + 0xF9C)
 
#define NSS_TSEN_CALIBRATION_TIMESTAMP   (EEPROM_START + 0xFD4)
 
#define NSS_IAP_ENTRY   0x1FFF1FF1
 
#define NSS_I2C_BASE   0x40000000
 
#define NSS_WWDT_BASE   0x40004000
 
#define NSS_TIMER16_0_BASE   0x4000C000
 
#define NSS_TIMER32_0_BASE   0x40014000
 
#define NSS_FLASH_BASE   0x4003C000
 
#define NSS_EEPROM_BASE   0x40034000
 
#define NSS_PMU_BASE   0x40038000
 
#define NSS_SSP0_BASE   0x40040000
 
#define NSS_IOCON_BASE   0x40044000
 
#define NSS_SYSCON_BASE   0x40048000
 
#define NSS_RTC_BASE   0x40054000
 
#define NSS_NFC_BASE   0x40058000
 
#define NSS_TSEN_BASE   0x40060000
 
#define NSS_GPIO_BASE   0x50000000
 
#define NSS_I2C   ((NSS_I2C_T *) NSS_I2C_BASE)
 
#define NSS_WWDT   ((NSS_WWDT_T *) NSS_WWDT_BASE)
 
#define NSS_TIMER16_0   ((NSS_TIMER_T *) NSS_TIMER16_0_BASE)
 
#define NSS_TIMER32_0   ((NSS_TIMER_T *) NSS_TIMER32_0_BASE)
 
#define NSS_FLASH   ((NSS_FLASH_T *) NSS_FLASH_BASE)
 
#define NSS_EEPROM   ((NSS_EEPROM_T*) NSS_EEPROM_BASE)
 
#define NSS_PMU   ((NSS_PMU_T *) NSS_PMU_BASE)
 
#define NSS_SSP0   ((NSS_SSP_T *) NSS_SSP0_BASE)
 
#define NSS_IOCON   ((NSS_IOCON_T *) NSS_IOCON_BASE)
 
#define NSS_SYSCON   ((NSS_SYSCON_T*) NSS_SYSCON_BASE)
 
#define NSS_RTC   ((NSS_RTC_T *) NSS_RTC_BASE)
 
#define NSS_NFC   ((NSS_NFC_T *) NSS_NFC_BASE)
 
#define NSS_TSEN   ((NSS_TSEN_T *) NSS_TSEN_BASE)
 
#define NSS_GPIO   ((NSS_GPIO_T *) NSS_GPIO_BASE)
 
#define NSS_NFC_UID   ((NFC_UID_T *) NSS_NFC_UID_BASE)
 
#define Chip_TIMER16_0_Init()   Chip_TIMER_Init(NSS_TIMER16_0, CLOCK_PERIPHERAL_16TIMER0)
 
#define Chip_TIMER16_0_DeInit()   Chip_TIMER_DeInit(NSS_TIMER16_0, CLOCK_PERIPHERAL_16TIMER0)
 
#define Chip_TIMER32_0_Init()   Chip_TIMER_Init(NSS_TIMER32_0, CLOCK_PERIPHERAL_32TIMER0)
 
#define Chip_TIMER32_0_DeInit()   Chip_TIMER_DeInit(NSS_TIMER32_0, CLOCK_PERIPHERAL_32TIMER0)
 

Data Structure Documentation

◆ NFC_UID_T

struct NFC_UID_T

NFC ID mapping. Structure allows byte-by-byte access to the same memory region.

Data Fields
uint8_t bytes[8]

Use for byte-by-byte access

Macro Definition Documentation

◆ ASSERT

#define ASSERT (   expr)    /* Prevent a compiler warning for unused variables */

If condition expr is false, the debugger halts (BKPT instruction), otherwise does nothing.

Parameters
expr: the condition to check
Note
If the macro DEBUG is not defined, the ASSERT macro generates no code.
If the expression expr has side-effects, the program behaves differently depending on whether DEBUG is defined.

◆ SDK_VERSION

#define SDK_VERSION   12_4_nhs3100

SDK version information

◆ NSS_SFRO_FREQUENCY

#define NSS_SFRO_FREQUENCY   8000000

System Free-Running Oscillator (SFRO) frequency in Hz

◆ NSS_TFRO_FREQUENCY

#define NSS_TFRO_FREQUENCY   32768

Timer Oscillator (TFRO) frequency in Hz

◆ EEPROM_START

#define EEPROM_START   0x30000000

EEPROM start address

◆ EEPROM_ROW_SIZE

#define EEPROM_ROW_SIZE   64

The EEPROM is organized in rows, this is the row size (in bytes)

◆ EEPROM_NR_OF_R_ROWS

#define EEPROM_NR_OF_R_ROWS   64

Complete EEPROM area is readable

◆ EEPROM_NR_OF_RW_ROWS

#define EEPROM_NR_OF_RW_ROWS   58

Last 6 rows (384 bytes) are read-only, so we only publish 58 rows

◆ FLASH_START

#define FLASH_START   0

FLASH start address

◆ FLASH_SECTOR_SIZE

#define FLASH_SECTOR_SIZE   1024

The FLASH is organized in sectors, this is the sector size (in bytes)

◆ FLASH_PAGE_SIZE

#define FLASH_PAGE_SIZE   64

Each FLASH sector is organized in pages, this is the page size (in bytes)

◆ FLASH_PAGES_PER_SECTOR

#define FLASH_PAGES_PER_SECTOR   (FLASH_SECTOR_SIZE / FLASH_PAGE_SIZE)

Sector size in number of pages.

◆ FLASH_NR_OF_R_SECTORS

#define FLASH_NR_OF_R_SECTORS   32

Complete FLASH area is readable

◆ FLASH_NR_OF_RW_SECTORS

#define FLASH_NR_OF_RW_SECTORS   30

Last 2 sectors (2048 bytes) are read-only, so we only publish 30 sectors

◆ NSS_NFC_UID_BASE

#define NSS_NFC_UID_BASE   (EEPROM_START + 0xF9C)

Base address of the NFC unique ID (same value can be found in the NFC tag header and read via NFC)

◆ NSS_TSEN_CALIBRATION_TIMESTAMP

#define NSS_TSEN_CALIBRATION_TIMESTAMP   (EEPROM_START + 0xFD4)

Location of the tsen calibration timestamp

◆ NSS_IAP_ENTRY

#define NSS_IAP_ENTRY   0x1FFF1FF1

In-Application-Programming entry address

◆ NSS_I2C_BASE

#define NSS_I2C_BASE   0x40000000

Base address of the I2C peripheral

◆ NSS_WWDT_BASE

#define NSS_WWDT_BASE   0x40004000

Base address of the Watchdog Timer peripheral

◆ NSS_TIMER16_0_BASE

#define NSS_TIMER16_0_BASE   0x4000C000

Base address of the Timer0 16-bit peripheral

◆ NSS_TIMER32_0_BASE

#define NSS_TIMER32_0_BASE   0x40014000

Base address of the Timer0 32-bit peripheral

◆ NSS_FLASH_BASE

#define NSS_FLASH_BASE   0x4003C000

Base address of the Flash memory controller

◆ NSS_EEPROM_BASE

#define NSS_EEPROM_BASE   0x40034000

Base address of the EEPROM memory controller

◆ NSS_PMU_BASE

#define NSS_PMU_BASE   0x40038000

Base address of the Power Management Unit

◆ NSS_SSP0_BASE

#define NSS_SSP0_BASE   0x40040000

Base address of the Synchronous Serial Port peripheral

◆ NSS_IOCON_BASE

#define NSS_IOCON_BASE   0x40044000

Base address of the I/O configuration

◆ NSS_SYSCON_BASE

#define NSS_SYSCON_BASE   0x40048000

Base address of the System configuration

◆ NSS_RTC_BASE

#define NSS_RTC_BASE   0x40054000

Base address of the Real-Time-Clock peripheral

◆ NSS_NFC_BASE

#define NSS_NFC_BASE   0x40058000

Base address of the Near-Field Communication peripheral

◆ NSS_TSEN_BASE

#define NSS_TSEN_BASE   0x40060000

Base address of the Temperature sensor peripheral

◆ NSS_GPIO_BASE

#define NSS_GPIO_BASE   0x50000000

Base address of the General Purpose I/O peripheral

◆ NSS_I2C

#define NSS_I2C   ((NSS_I2C_T *) NSS_I2C_BASE)

Handle for the I2C peripheral

◆ NSS_WWDT

#define NSS_WWDT   ((NSS_WWDT_T *) NSS_WWDT_BASE)

Handle for the Watchdog Timer peripheral

◆ NSS_TIMER16_0

#define NSS_TIMER16_0   ((NSS_TIMER_T *) NSS_TIMER16_0_BASE)

Handle for the Timer0 16-bit peripheral

◆ NSS_TIMER32_0

#define NSS_TIMER32_0   ((NSS_TIMER_T *) NSS_TIMER32_0_BASE)

Handle for the Timer0 32-bit peripheral

◆ NSS_FLASH

#define NSS_FLASH   ((NSS_FLASH_T *) NSS_FLASH_BASE)

Handle for the Flash memory controller

◆ NSS_EEPROM

#define NSS_EEPROM   ((NSS_EEPROM_T*) NSS_EEPROM_BASE)

Handle for the EEPROM memory controller

◆ NSS_PMU

#define NSS_PMU   ((NSS_PMU_T *) NSS_PMU_BASE)

Handle for the Power Management Unit

◆ NSS_SSP0

#define NSS_SSP0   ((NSS_SSP_T *) NSS_SSP0_BASE)

Handle for the Synchronous Serial Port peripheral

◆ NSS_IOCON

#define NSS_IOCON   ((NSS_IOCON_T *) NSS_IOCON_BASE)

Handle for the I/O configuration

◆ NSS_SYSCON

#define NSS_SYSCON   ((NSS_SYSCON_T*) NSS_SYSCON_BASE)

Handle for the System configuration

◆ NSS_RTC

#define NSS_RTC   ((NSS_RTC_T *) NSS_RTC_BASE)

Handle for the Real-Time-Clock peripheral

◆ NSS_NFC

#define NSS_NFC   ((NSS_NFC_T *) NSS_NFC_BASE)

Handle for the Near-Field Communication peripheral

◆ NSS_TSEN

#define NSS_TSEN   ((NSS_TSEN_T *) NSS_TSEN_BASE)

Handle for the Temperature sensor peripheral

◆ NSS_GPIO

#define NSS_GPIO   ((NSS_GPIO_T *) NSS_GPIO_BASE)

Handle for the General Purpose I/O peripheral

◆ NSS_NFC_UID

#define NSS_NFC_UID   ((NFC_UID_T *) NSS_NFC_UID_BASE)

Pointer to a copy of the NFC ID, accessible by the ARM. The NFC ID stored in the NFC controller is not accessible by the ARM.

Note
This value is stored in the (RO part of the) EEPROM. EEPROM must be initialized before accessing. See Chip_EEPROM_Init

◆ Chip_TIMER16_0_Init

#define Chip_TIMER16_0_Init ( )    Chip_TIMER_Init(NSS_TIMER16_0, CLOCK_PERIPHERAL_16TIMER0)

Helper function for Timer16_0 Init

◆ Chip_TIMER16_0_DeInit

#define Chip_TIMER16_0_DeInit ( )    Chip_TIMER_DeInit(NSS_TIMER16_0, CLOCK_PERIPHERAL_16TIMER0)

Helper function for Timer16_0 DeInit

◆ Chip_TIMER32_0_Init

#define Chip_TIMER32_0_Init ( )    Chip_TIMER_Init(NSS_TIMER32_0, CLOCK_PERIPHERAL_32TIMER0)

Helper function for Timer32_0 Init

◆ Chip_TIMER32_0_DeInit

#define Chip_TIMER32_0_DeInit ( )    Chip_TIMER_DeInit(NSS_TIMER32_0, CLOCK_PERIPHERAL_32TIMER0)

Helper function for Timer32_0 DeInit