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NHS31xx SW API
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This driver provides APIs for the configuration and operation of the SSP hardware block. The SSP interface provides four operating modes:
The SSP Driver supports data transfer on SPI, 4-wire SSI or Microwire buses. There can be multiple masters and slaves on the bus, though only one master and slave can communicate with each other at a given point in time. The SSP hardware block supports full-duplex data transfer of frames of length 4 bits to 16 bits. The driver supports both polled or interrupt based operation. Refer Polling Mode Usage for polling mode usage and Interrupt Mode Usage for interrupt mode usage
Data Structures | |
struct | NSS_SSP_T |
struct | Chip_SSP_DATA_SETUP_T |
Macros | |
#define | SSP_CR0_DSS(n) ((uint32_t) ((n) & 0xF)) |
#define | SSP_CR0_FRF_SPI ((uint32_t) (0 << 4)) |
#define | SSP_CR0_FRF_TI ((uint32_t) (1 << 4)) |
#define | SSP_CR0_FRF_MICROWIRE ((uint32_t) (2 << 4)) |
#define | SSP_CR0_CPOL_LO ((uint32_t) (0)) |
#define | SSP_CR0_CPOL_HI ((uint32_t) (1 << 6)) |
#define | SSP_CR0_CPHA_FIRST ((uint32_t) (0)) |
#define | SSP_CR0_CPHA_SECOND ((uint32_t) (1 << 7)) |
#define | SSP_CR0_SCR(n) ((uint32_t) ((n & 0xFF) << 8)) |
#define | SSP_CR0_BITMASK ((uint32_t) (0xFFFF)) |
#define | SSP_CR1_LBM_EN ((uint32_t) (1 << 0)) |
#define | SSP_CR1_SSP_EN ((uint32_t) (1 << 1)) |
#define | SSP_CR1_SLAVE_EN ((uint32_t) (1 << 2)) |
#define | SSP_CR1_MASTER_EN ((uint32_t) (0)) |
#define | SSP_CR1_SO_DISABLE ((uint32_t) (1 << 3)) |
#define | SSP_CR1_BITMASK ((uint32_t) (0x0F)) |
#define | SSP_CPSR_BITMASK ((uint32_t) (0xFF)) |
#define | SSP_DR_BITMASK(n) ((n) & 0xFFFF) |
#define | SSP_SR_BITMASK ((uint32_t) (0x1F)) |
#define | SSP_ICR_BITMASK ((uint32_t) (0x03)) |
Enumerations | |
enum | SSP_INT_STATUS_T { RESET = 0, SET = !RESET } |
enum | Status { ERROR = 0, SUCCESS = !ERROR } |
enum | SSP_STATUS_T { SSP_STAT_TFE = ((uint32_t)(1 << 0)), SSP_STAT_TNF = ((uint32_t)(1 << 1)), SSP_STAT_RNE = ((uint32_t)(1 << 2)), SSP_STAT_RFF = ((uint32_t)(1 << 3)), SSP_STAT_BSY = ((uint32_t)(1 << 4)) } |
enum | SSP_INTMASK_T { SSP_RORIM = ((uint32_t)(1 << 0)), SSP_RTIM = ((uint32_t)(1 << 1)), SSP_RXIM = ((uint32_t)(1 << 2)), SSP_TXIM = ((uint32_t)(1 << 3)), SSP_INT_MASK_BITMASK = ((uint32_t)(0xF)) } |
enum | SSP_MASKINTSTATUS_T { SSP_RORMIS = ((uint32_t)(1 << 0)), SSP_RTMIS = ((uint32_t)(1 << 1)), SSP_RXMIS = ((uint32_t)(1 << 2)), SSP_TXMIS = ((uint32_t)(1 << 3)), SSP_MASK_INT_STAT_BITMASK = ((uint32_t)(0xF)) } |
enum | SSP_RAWINTSTATUS_T { SSP_RORRIS = ((uint32_t)(1 << 0)), SSP_RTRIS = ((uint32_t)(1 << 1)), SSP_RXRIS = ((uint32_t)(1 << 2)), SSP_TXRIS = ((uint32_t)(1 << 3)), SSP_RAW_INT_STAT_BITMASK = ((uint32_t)(0xF)) } |
enum | SSP_INTCLEAR_T { SSP_RORIC = 0x0, SSP_RTIC = 0x1, SSP_INT_CLEAR_BITMASK = 0x3 } |
enum | CHIP_SSP_CLOCK_MODE_T { SSP_CLOCK_CPHA0_CPOL0 = (0 << 6), SSP_CLOCK_CPHA0_CPOL1 = (1u << 6), SSP_CLOCK_CPHA1_CPOL0 = (2u << 6), SSP_CLOCK_CPHA1_CPOL1 = (3u << 6), SSP_CLOCK_MODE0 = SSP_CLOCK_CPHA0_CPOL0, SSP_CLOCK_MODE1 = SSP_CLOCK_CPHA1_CPOL0, SSP_CLOCK_MODE2 = SSP_CLOCK_CPHA0_CPOL1, SSP_CLOCK_MODE3 = SSP_CLOCK_CPHA1_CPOL1 } |
enum | CHIP_SSP_FRAME_FORMAT_T { SSP_FRAME_FORMAT_SPI = (0 << 4), SSP_FRAME_FORMAT_TI = (1u << 4), SSP_FRAME_FORMAT_MICROWIRE = (2u << 4) } |
enum | CHIP_SSP_BITS_T { SSP_BITS_4 = (3u << 0), SSP_BITS_5 = (4u << 0), SSP_BITS_6 = (5u << 0), SSP_BITS_7 = (6u << 0), SSP_BITS_8 = (7u << 0), SSP_BITS_9 = (8u << 0), SSP_BITS_10 = (9u << 0), SSP_BITS_11 = (10u << 0), SSP_BITS_12 = (11u << 0), SSP_BITS_13 = (12u << 0), SSP_BITS_14 = (13u << 0), SSP_BITS_15 = (14u << 0), SSP_BITS_16 = (15u << 0) } |
enum | CHIP_SSP_MODE_T { SSP_MODE_MASTER = (0 << 2), SSP_MODE_SLAVE = (1u << 2) } |
struct NSS_SSP_T |
SSP register block structure
Data Fields | ||
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__IO uint32_t | CR0 |
Control Register 0. Selects the serial clock rate, bus type, and data size. |
__IO uint32_t | CR1 |
Control Register 1. Selects master/slave and other modes. |
__IO uint32_t | DR |
Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. |
__I uint32_t | SR |
Status Register |
__IO uint32_t | CPSR |
Clock Prescale Register |
__IO uint32_t | IMSC |
Interrupt Mask Set and Clear Register |
__I uint32_t | RIS |
Raw Interrupt Status Register |
__I uint32_t | MIS |
Masked Interrupt Status Register |
__O uint32_t | ICR |
SSPICR Interrupt Clear Register |
struct Chip_SSP_DATA_SETUP_T |
#define SSP_CR0_DSS | ( | n | ) | ((uint32_t) ((n) & 0xF)) |
SSP data size select, must be 4 bits to 16 bits
#define SSP_CR0_FRF_SPI ((uint32_t) (0 << 4)) |
SSP control 0 Motorola SPI mode
#define SSP_CR0_FRF_TI ((uint32_t) (1 << 4)) |
SSP control 0 TI synchronous serial mode
#define SSP_CR0_FRF_MICROWIRE ((uint32_t) (2 << 4)) |
SSP control 0 National Micro-wire mode
#define SSP_CR0_CPOL_LO ((uint32_t) (0)) |
SPI clock polarity bit Low (used in SPI mode only), maintains the bus clock low between frames
#define SSP_CR0_CPOL_HI ((uint32_t) (1 << 6)) |
SPI clock polarity bit High (used in SPI mode only), maintains the bus clock high between frames
#define SSP_CR0_CPHA_FIRST ((uint32_t) (0)) |
SPI clock out phase bit FIRST(used in SPI mode only), captures data on the first clock transition of the frame
#define SSP_CR0_CPHA_SECOND ((uint32_t) (1 << 7)) |
SPI clock out phase bit SECOND (used in SPI mode only), captures data on the second clock transition of the frame
#define SSP_CR0_SCR | ( | n | ) | ((uint32_t) ((n & 0xFF) << 8)) |
SSP serial clock rate value load macro, divider rate is PERIPH_CLK / (cpsr * (SCR + 1))
#define SSP_CR0_BITMASK ((uint32_t) (0xFFFF)) |
SSP CR0 bit mask
#define SSP_CR1_LBM_EN ((uint32_t) (1 << 0)) |
SSP control 1 loopback mode enable bit
#define SSP_CR1_SSP_EN ((uint32_t) (1 << 1)) |
SSP control 1 enable bit
#define SSP_CR1_SLAVE_EN ((uint32_t) (1 << 2)) |
SSP control 1 slave enable
#define SSP_CR1_MASTER_EN ((uint32_t) (0)) |
SSP control 1 master enable
#define SSP_CR1_SO_DISABLE ((uint32_t) (1 << 3)) |
SSP control 1 slave out disable bit, disables transmit line in slave mode
#define SSP_CR1_BITMASK ((uint32_t) (0x0F)) |
SSP CR1 bit mask
#define SSP_CPSR_BITMASK ((uint32_t) (0xFF)) |
SSP CPSR bit mask
#define SSP_DR_BITMASK | ( | n | ) | ((n) & 0xFFFF) |
SSP data bit mask
#define SSP_SR_BITMASK ((uint32_t) (0x1F)) |
SSP SR bit mask
#define SSP_ICR_BITMASK ((uint32_t) (0x03)) |
ICR bit mask
enum SSP_INT_STATUS_T |
enum Status |
enum SSP_STATUS_T |
enum SSP_INTMASK_T |
enum SSP_MASKINTSTATUS_T |
enum SSP_RAWINTSTATUS_T |
enum SSP_INTCLEAR_T |
SSP clock format
Enumerator | |
---|---|
SSP_CLOCK_CPHA0_CPOL0 | CPHA = 0, CPOL = 0 |
SSP_CLOCK_CPHA0_CPOL1 | CPHA = 0, CPOL = 1 |
SSP_CLOCK_CPHA1_CPOL0 | CPHA = 1, CPOL = 0 |
SSP_CLOCK_CPHA1_CPOL1 | CPHA = 1, CPOL = 1 |
SSP_CLOCK_MODE0 | alias for SSP_CLOCK_CPHA0_CPOL0 |
SSP_CLOCK_MODE1 | alias for SSP_CLOCK_CPHA1_CPOL0 |
SSP_CLOCK_MODE2 | alias for SSP_CLOCK_CPHA0_CPOL1 |
SSP_CLOCK_MODE3 | alias for SSP_CLOCK_CPHA1_CPOL1 |
enum CHIP_SSP_BITS_T |
Number of bits per frame
enum CHIP_SSP_MODE_T |
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inlinestatic |
Enable SSP operation
pSSP | : The base address of the SSP peripheral on the chip |
< SSP control 1 enable bit
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inlinestatic |
Disable SSP operation
pSSP | : The base address of the SSP peripheral on the chip |
< SSP control 1 enable bit
< SSP CR1 bit mask
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inlinestatic |
Enable loopback mode
pSSP | : The base address of the SSP peripheral on the chip |
< SSP control 1 loopback mode enable bit
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inlinestatic |
Disable loopback mode
pSSP | : The base address of the SSP peripheral on the chip |
< SSP control 1 loopback mode enable bit
< SSP CR1 bit mask
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inlinestatic |
Get the current status of SSP controller
pSSP | : The base address of the SSP peripheral on the chip |
Stat | : Type of status, as given below : |
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inlinestatic |
Get the masked interrupt status
pSSP | : The base address of the SSP peripheral on the chip |
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inlinestatic |
Get the raw interrupt status
pSSP | : The base address of the SSP peripheral on the chip |
RawInt | : Interrupt condition to get status for, as given below : |
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inlinestatic |
Get the number of bits transferred in each frame
pSSP | : The base address of the SSP peripheral on the chip |
< SSP data size select, must be 4 bits to 16 bits
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inlinestatic |
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inlinestatic |
Enable interrupt for the SSP
pSSP | : The base address of the SSP peripheral on the chip |
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inlinestatic |
Disable interrupt for the SSP
pSSP | : The base address of the SSP peripheral on the chip |
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inlinestatic |
Get received 16-bit SSP data
pSSP | : The base address of the SSP peripheral on the chip |
< SSP data bit mask
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inlinestatic |
Send SSP 16-bit data
pSSP | : The base address of the SSP peripheral on the chip |
tx_data | : SSP 16-bit data to be transmitted |
< SSP data bit mask
void Chip_SSP_SetClockRate | ( | NSS_SSP_T * | pSSP, |
uint32_t | clk_rate, | ||
uint32_t | prescale | ||
) |
Set up output clocks per bit for SSP bus
pSSP | : The base address of the SSP peripheral on the chip |
clk_rate | fs: The number of prescaler-output clocks per bit on the bus, minus one |
prescale | : The factor by which the Prescaler divides the SSP peripheral clock PCLK |
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inlinestatic |
Set up the SSP frame format
pSSP | : The base address of the SSP peripheral on the chip |
bits | : The number of bits transferred in each frame, should be between SSP_BITS_4 and SSP_BITS_16 |
frameFormat | : Frame format, as given below : |
clockMode | : Select Clock polarity and Clock phase, as given below : |
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inlinestatic |
Set the SSP working as master or slave mode
pSSP | : The base address of the SSP peripheral on the chip |
mode | : Operating mode, as given below: |
void Chip_SSP_Int_FlushData | ( | NSS_SSP_T * | pSSP | ) |
Clean all data in RX FIFO of SSP
pSSP | : The base address of the SSP peripheral on the chip |
Status Chip_SSP_Int_RWFrames8Bits | ( | NSS_SSP_T * | pSSP, |
Chip_SSP_DATA_SETUP_T * | xf_setup | ||
) |
SSP Interrupt Read/Write with 8-bit frame width
pSSP | : The base address of the SSP peripheral on the chip |
xf_setup | : Pointer to a SSP_DATA_SETUP_T structure that contains specified information about transmit/receive data configuration |
Status Chip_SSP_Int_RWFrames16Bits | ( | NSS_SSP_T * | pSSP, |
Chip_SSP_DATA_SETUP_T * | xf_setup | ||
) |
SSP Interrupt Read/Write with 16-bit frame width
pSSP | : The base address of the SSP peripheral on the chip |
xf_setup | : Pointer to a SSP_DATA_SETUP_T structure that contains specified information about transmit/receive data configuration |
uint32_t Chip_SSP_RWFrames_Blocking | ( | NSS_SSP_T * | pSSP, |
Chip_SSP_DATA_SETUP_T * | xf_setup | ||
) |
SSP Polling Read/Write in blocking mode
pSSP | : The base address of the SSP peripheral on the chip |
xf_setup | : Pointer to a SSP_DATA_SETUP_T structure that contains specified information about transmit/receive data configuration |
uint32_t Chip_SSP_WriteFrames_Blocking | ( | NSS_SSP_T * | pSSP, |
uint8_t * | buffer, | ||
uint32_t | buffer_len | ||
) |
SSP Polling Write in blocking mode
pSSP | : The base address of the SSP peripheral on the chip |
buffer | : Buffer address |
buffer_len | : Buffer length |
uint32_t Chip_SSP_ReadFrames_Blocking | ( | NSS_SSP_T * | pSSP, |
uint8_t * | buffer, | ||
uint32_t | buffer_len | ||
) |
SSP Polling Read in blocking mode
pSSP | : The base address of the SSP peripheral on the chip |
buffer | : Buffer address |
buffer_len | : The length of buffer |
void Chip_SSP_Init | ( | NSS_SSP_T * | pSSP | ) |
Initialize the SSP
pSSP | : The base address of the SSP peripheral on the chip |
void Chip_SSP_DeInit | ( | NSS_SSP_T * | pSSP | ) |
De-initialise the SSP
pSSP | : The base address of the SSP peripheral on the chip |
void Chip_SSP_SetMaster | ( | NSS_SSP_T * | pSSP, |
bool | master | ||
) |
Set the SSP operating modes, master or slave
pSSP | : The base address of the SSP peripheral on the chip |
master | : 1 to set master, 0 to set slave |
void Chip_SSP_SetBitRate | ( | NSS_SSP_T * | pSSP, |
uint32_t | bitRate | ||
) |
Set the clock frequency for SSP interface
pSSP | : The base address of the SSP peripheral on the chip |
bitRate | : The SSP bit rate in bits per seconds |
uint32_t Chip_SSP_GetBitRate | ( | NSS_SSP_T * | pSSP | ) |
Get the clock frequency for SSP interface
pSSP | : The base address of the SSP peripheral on the chip |