24 #ifndef __CORE_CMFUNC_H 25 #define __CORE_CMFUNC_H 34 #if defined ( __CC_ARM ) 37 #if (__ARMCC_VERSION < 400677) 38 #error "Please use ARM Compiler Toolchain V4.0.677 or later!" 52 register uint32_t __regControl
__ASM(
"control");
65 register uint32_t __regControl
__ASM(
"control");
66 __regControl = control;
78 register uint32_t __regIPSR
__ASM(
"ipsr");
91 register uint32_t __regAPSR
__ASM(
"apsr");
104 register uint32_t __regXPSR
__ASM(
"xpsr");
117 register uint32_t __regProcessStackPointer
__ASM(
"psp");
118 return(__regProcessStackPointer);
130 register uint32_t __regProcessStackPointer
__ASM(
"psp");
131 __regProcessStackPointer = topOfProcStack;
143 register uint32_t __regMainStackPointer
__ASM(
"msp");
144 return(__regMainStackPointer);
156 register uint32_t __regMainStackPointer
__ASM(
"msp");
157 __regMainStackPointer = topOfMainStack;
169 register uint32_t __regPriMask
__ASM(
"primask");
170 return(__regPriMask);
182 register uint32_t __regPriMask
__ASM(
"primask");
183 __regPriMask = (priMask);
187 #if (__CORTEX_M >= 0x03) 194 #define __enable_fault_irq __enable_fiq 202 #define __disable_fault_irq __disable_fiq 213 register uint32_t __regBasePri
__ASM(
"basepri");
214 return(__regBasePri);
226 register uint32_t __regBasePri
__ASM(
"basepri");
227 __regBasePri = (basePri & 0xff);
239 register uint32_t __regFaultMask
__ASM(
"faultmask");
240 return(__regFaultMask);
252 register uint32_t __regFaultMask
__ASM(
"faultmask");
253 __regFaultMask = (faultMask & (uint32_t)1);
259 #if (__CORTEX_M == 0x04) 269 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) 270 register uint32_t __regfpscr
__ASM(
"fpscr");
286 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) 287 register uint32_t __regfpscr
__ASM(
"fpscr");
288 __regfpscr = (fpscr);
295 #elif defined ( __ICCARM__ ) 298 #include <cmsis_iar.h> 301 #elif defined ( __TMS470__ ) 304 #include <cmsis_ccs.h> 307 #elif defined ( __GNUC__ ) 317 __ASM volatile (
"cpsie i");
328 __ASM volatile (
"cpsid i");
342 __ASM volatile (
"MRS %0, control" :
"=r" (result) );
355 __ASM volatile (
"MSR control, %0" : :
"r" (control) );
369 __ASM volatile (
"MRS %0, ipsr" :
"=r" (result) );
384 __ASM volatile (
"MRS %0, apsr" :
"=r" (result) );
399 __ASM volatile (
"MRS %0, xpsr" :
"=r" (result) );
412 register uint32_t result;
414 __ASM volatile (
"MRS %0, psp\n" :
"=r" (result) );
427 __ASM volatile (
"MSR psp, %0\n" : :
"r" (topOfProcStack) );
439 register uint32_t result;
441 __ASM volatile (
"MRS %0, msp\n" :
"=r" (result) );
454 __ASM volatile (
"MSR msp, %0\n" : :
"r" (topOfMainStack) );
468 __ASM volatile (
"MRS %0, primask" :
"=r" (result) );
481 __ASM volatile (
"MSR primask, %0" : :
"r" (priMask) );
485 #if (__CORTEX_M >= 0x03) 492 __attribute__( ( always_inline ) )
__STATIC_INLINE void __enable_fault_irq(
void)
494 __ASM volatile (
"cpsie f");
503 __attribute__( ( always_inline ) )
__STATIC_INLINE void __disable_fault_irq(
void)
505 __ASM volatile (
"cpsid f");
515 __attribute__( ( always_inline ) )
__STATIC_INLINE uint32_t __get_BASEPRI(
void)
519 __ASM volatile (
"MRS %0, basepri_max" :
"=r" (result) );
530 __attribute__( ( always_inline ) )
__STATIC_INLINE void __set_BASEPRI(uint32_t value)
532 __ASM volatile (
"MSR basepri, %0" : :
"r" (value) );
542 __attribute__( ( always_inline ) )
__STATIC_INLINE uint32_t __get_FAULTMASK(
void)
546 __ASM volatile (
"MRS %0, faultmask" :
"=r" (result) );
557 __attribute__( ( always_inline ) )
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
559 __ASM volatile (
"MSR faultmask, %0" : :
"r" (faultMask) );
565 #if (__CORTEX_M == 0x04) 573 __attribute__( ( always_inline ) )
__STATIC_INLINE uint32_t __get_FPSCR(
void)
575 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) 578 __ASM volatile (
"VMRS %0, fpscr" :
"=r" (result) );
592 __attribute__( ( always_inline ) )
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
594 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) 595 __ASM volatile (
"VMSR fpscr, %0" : :
"r" (fpscr) );
602 #elif defined ( __TASKING__ ) #define __STATIC_INLINE
Definition: core_cm0plus.h:78
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
Set Priority Mask.
Definition: core_cmFunc.h:479
__STATIC_INLINE uint32_t __get_PSP(void)
Get Process Stack Pointer.
Definition: core_cmFunc.h:410
__STATIC_INLINE uint32_t __get_CONTROL(void)
Get Control Register.
Definition: core_cmFunc.h:338
__STATIC_INLINE uint32_t __get_IPSR(void)
Get IPSR Register.
Definition: core_cmFunc.h:365
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
Set Process Stack Pointer.
Definition: core_cmFunc.h:425
#define __ASM
Definition: core_cm0plus.h:76
__STATIC_INLINE uint32_t __get_PRIMASK(void)
Get Priority Mask.
Definition: core_cmFunc.h:464
__STATIC_INLINE void __enable_irq(void)
Enable IRQ Interrupts.
Definition: core_cmFunc.h:315
__STATIC_INLINE uint32_t __get_MSP(void)
Get Main Stack Pointer.
Definition: core_cmFunc.h:437
__STATIC_INLINE uint32_t __get_xPSR(void)
Get xPSR Register.
Definition: core_cmFunc.h:395
__STATIC_INLINE uint32_t __get_APSR(void)
Get APSR Register.
Definition: core_cmFunc.h:380
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
Set Main Stack Pointer.
Definition: core_cmFunc.h:452
__STATIC_INLINE void __set_CONTROL(uint32_t control)
Set Control Register.
Definition: core_cmFunc.h:353
__STATIC_INLINE void __disable_irq(void)
Disable IRQ Interrupts.
Definition: core_cmFunc.h:326