NHS31xx SW API
eeprom_nss.h
1 /*
2  * Copyright 2014-2019 NXP
3  * This software is owned or controlled by NXP and may only be used strictly
4  * in accordance with the applicable license terms. By expressly accepting
5  * such terms or by downloading, installing, activating and/or otherwise using
6  * the software, you are agreeing that you have read, and that you agree to
7  * comply with and are bound by, such license terms. If you do not agree to
8  * be bound by the applicable license terms, then you may not retain, install,
9  * activate or otherwise use the software.
10  */
11 
12 #ifndef __EEPROM_NSS_H_
13 #define __EEPROM_NSS_H_
14 
57 #include "chip.h"
58 
60 typedef struct NSS_EEPROM_S {
61  __IO uint32_t CMD;
62  __I uint32_t RESERVED1; /* next field at offset 0x08 */
63  __IO uint32_t RWSTATE;
64  __IO uint32_t PAUTOPROG;
65  __IO uint32_t WSTATE;
66  __IO uint32_t CLKDIV;
67  __IO uint32_t PWRDWN;
68  __I uint32_t RESERVED2; /* next field at offset 0x20 */
69  __IO uint32_t MSSTART;
70  __IO uint32_t MSSTOP;
71  __I uint32_t MSDATASIG;
72  __I uint32_t MSPARSIG;
73  __I uint32_t RESERVED3; /* next field at offset 0x34 */
74  __I uint32_t STATUS;
75  __I uint32_t RESERVED4[998]; /* next field at offset 0xFD0 */
76  __I uint32_t MODULE_CONFIG;
77  __I uint32_t RESERVED5; /* next field at offset 0xFD8 */
78  __IO uint32_t INT_CLR_ENABLE;
79  __IO uint32_t INT_SET_ENABLE;
80  __I uint32_t INT_STATUS;
81  __I uint32_t INT_ENABLE;
82  __IO uint32_t INT_CLR_STATUS;
83  __IO uint32_t INT_SET_STATUS;
84  __I uint32_t RESERVED6[3]; /* next field at offset 0xFFC */
85  __IO uint32_t MODULE_ID;
86 } NSS_EEPROM_T;
87 
100 void Chip_EEPROM_Init(NSS_EEPROM_T *pEEPROM);
101 
108 void Chip_EEPROM_DeInit(NSS_EEPROM_T *pEEPROM);
109 
120 void Chip_EEPROM_Read(NSS_EEPROM_T *pEEPROM, int offset, void *pBuf, int size);
121 
137 void Chip_EEPROM_Write(NSS_EEPROM_T *pEEPROM, int offset, const void *pBuf, int size);
138 
154 void Chip_EEPROM_Memset(NSS_EEPROM_T *pEEPROM, int offset, uint8_t pattern, int size);
155 
163 void Chip_EEPROM_Flush(NSS_EEPROM_T *pEEPROM, bool wait);
164 
165 #endif
volatile uint32_t PAUTOPROG
Definition: eeprom_nss.h:64
volatile const uint32_t INT_ENABLE
Definition: eeprom_nss.h:81
volatile const uint32_t RESERVED5
Definition: eeprom_nss.h:77
void Chip_EEPROM_Flush(NSS_EEPROM_T *pEEPROM, bool wait)
volatile uint32_t PWRDWN
Definition: eeprom_nss.h:67
volatile uint32_t INT_CLR_STATUS
Definition: eeprom_nss.h:82
#define __IO
Definition: core_cm0plus.h:167
#define __I
Definition: core_cm0plus.h:164
volatile uint32_t MODULE_ID
Definition: eeprom_nss.h:85
volatile uint32_t CLKDIV
Definition: eeprom_nss.h:66
volatile const uint32_t MODULE_CONFIG
Definition: eeprom_nss.h:76
volatile const uint32_t MSPARSIG
Definition: eeprom_nss.h:72
Definition: eeprom_nss.h:60
void Chip_EEPROM_DeInit(NSS_EEPROM_T *pEEPROM)
volatile const uint32_t RESERVED2
Definition: eeprom_nss.h:68
volatile uint32_t MSSTART
Definition: eeprom_nss.h:69
volatile uint32_t CMD
Definition: eeprom_nss.h:61
volatile const uint32_t STATUS
Definition: eeprom_nss.h:74
void Chip_EEPROM_Read(NSS_EEPROM_T *pEEPROM, int offset, void *pBuf, int size)
volatile const uint32_t MSDATASIG
Definition: eeprom_nss.h:71
volatile uint32_t MSSTOP
Definition: eeprom_nss.h:70
void Chip_EEPROM_Init(NSS_EEPROM_T *pEEPROM)
volatile uint32_t WSTATE
Definition: eeprom_nss.h:65
volatile const uint32_t RESERVED3
Definition: eeprom_nss.h:73
volatile uint32_t INT_CLR_ENABLE
Definition: eeprom_nss.h:78
volatile uint32_t RWSTATE
Definition: eeprom_nss.h:63
void Chip_EEPROM_Write(NSS_EEPROM_T *pEEPROM, int offset, const void *pBuf, int size)
volatile const uint32_t INT_STATUS
Definition: eeprom_nss.h:80
volatile uint32_t INT_SET_STATUS
Definition: eeprom_nss.h:83
volatile uint32_t INT_SET_ENABLE
Definition: eeprom_nss.h:79
volatile const uint32_t RESERVED1
Definition: eeprom_nss.h:62
void Chip_EEPROM_Memset(NSS_EEPROM_T *pEEPROM, int offset, uint8_t pattern, int size)