NHS31xx SW API
iocon_nss.h
1 /*
2  * Copyright 2014-2016,2018-2019 NXP
3  * This software is owned or controlled by NXP and may only be used strictly
4  * in accordance with the applicable license terms. By expressly accepting
5  * such terms or by downloading, installing, activating and/or otherwise using
6  * the software, you are agreeing that you have read, and that you agree to
7  * comply with and are bound by, such license terms. If you do not agree to
8  * be bound by the applicable license terms, then you may not retain, install,
9  * activate or otherwise use the software.
10  */
11 
12 #ifndef __IOCON_NSS_H_
13 #define __IOCON_NSS_H_
14 
87 typedef struct NSS_IOCON_S {
88  __IO uint32_t REG[24];
89  __IO uint32_t RESERVED0[8]; /* next field at offset 0x080 */
90  __IO uint32_t ANABUSGROUND;
91 } NSS_IOCON_T;
92 
94 typedef enum IOCON_PIN {
95  IOCON_PIO0_0 = (0x000 >> 2),
96  IOCON_PIO0_1 = (0x004 >> 2),
97  IOCON_PIO0_2 = (0x008 >> 2),
98  IOCON_PIO0_3 = (0x00C >> 2),
99  IOCON_PIO0_4 = (0x010 >> 2),
100  IOCON_PIO0_5 = (0x014 >> 2),
101  IOCON_PIO0_6 = (0x018 >> 2),
102  IOCON_PIO0_7 = (0x01C >> 2),
103  IOCON_PIO0_8 = (0x020 >> 2),
104  IOCON_PIO0_9 = (0x024 >> 2),
105  IOCON_PIO0_10 = (0x028 >> 2),
106  IOCON_PIO0_11 = (0x02C >> 2),
108  IOCON_ANA0_0 = (0x030 >> 2),
109  IOCON_ANA0_1 = (0x034 >> 2),
110  IOCON_ANA0_2 = (0x038 >> 2),
111  IOCON_ANA0_3 = (0x03C >> 2),
112  IOCON_ANA0_4 = (0x040 >> 2),
113  IOCON_ANA0_5 = (0x044 >> 2),
114  IOCON_ANA0_6 = (0x048 >> 2),
115  IOCON_ANA0_7 = (0x04C >> 2),
116  IOCON_ANA0_8 = (0x050 >> 2),
117  IOCON_ANA0_9 = (0x054 >> 2),
118  IOCON_ANA0_10 = (0x058 >> 2),
119  IOCON_ANA0_11 = (0x05C >> 2),
120 } IOCON_PIN_T;
121 
123 typedef enum IOCON_ANABUS {
124  IOCON_ANABUS_EXT0 = (1 << 0),
125  IOCON_ANABUS_EXT1 = (1 << 1),
126  IOCON_ANABUS_EXT2 = (1 << 2),
127  IOCON_ANABUS_EXT3 = (1 << 3),
128  IOCON_ANABUS_EXT4 = (1 << 4),
129  IOCON_ANABUS_EXT5 = (1 << 5),
130  IOCON_ANABUS_EXT6 = (1 << 6),
131  IOCON_ANABUS_EXT7 = (1 << 7),
132  IOCON_ANABUS_EXT8 = (1 << 8),
133  IOCON_ANABUS_EXT9 = (1 << 9),
134  IOCON_ANABUS_EXT10 = (1 << 10),
135  IOCON_ANABUS_EXT11 = (1 << 11),
137  IOCON_ANABUS_INT0 = (1 << 12),
138  IOCON_ANABUS_INT1 = (1 << 13),
139  IOCON_ANABUS_INT2 = (1 << 14),
140  IOCON_ANABUS_INT3 = (1 << 15),
141  IOCON_ANABUS_INT4 = (1 << 16),
142  IOCON_ANABUS_INT5 = (1 << 17),
143  IOCON_ANABUS_INT6 = (1 << 18),
144  IOCON_ANABUS_INT7 = (1 << 19),
145  IOCON_ANABUS_INT8 = (1 << 20),
146  IOCON_ANABUS_INT9 = (1 << 21),
147  IOCON_ANABUS_INT10 = (1 << 22),
148  IOCON_ANABUS_INT11 = (1 << 23),
149  IOCON_ANABUS_INT12 = (1 << 24),
150  IOCON_ANABUS_INT13 = (1 << 25),
151  IOCON_ANABUS_INT14 = (1 << 26),
152  IOCON_ANABUS_INT15 = (1 << 27)
154 
155 #define IOCON_FUNC_0 (0x0)
156 #define IOCON_FUNC_1 (0x1)
157 #define IOCON_FUNC_2 (0x2)
158 #define IOCON_FUNC_3 (0x3)
159 #define IOCON_FUNC_4 (0x4)
160 #define IOCON_FUNC_5 (0x5)
161 #define IOCON_FUNC_6 (0x6)
162 #define IOCON_FUNC_7 (0x7)
163 #define IOCON_FUNC_MASK (0x7)
164 #define IOCON_RMODE_INACT (0x0 << 3)
165 #define IOCON_RMODE_PULLDOWN (0x1 << 3)
166 #define IOCON_RMODE_PULLUP (0x2 << 3)
167 #define IOCON_RMODE_REPEATER (0x3 << 3)
168 #define IOCON_RMODE_MASK (0x3 << 3)
169 #define IOCON_LPF_DISABLE (0x0 << 5)
170 #define IOCON_LPF_ENABLE (0x1 << 5)
171 #define IOCON_LPF_MASK (0x1 << 5)
172 #define IOCON_CDRIVE_FIXEDVOLTAGE (0x0 << 6)
173 #define IOCON_CDRIVE_PROGRAMMABLECURRENT (0x1 << 6)
175 #define IOCON_CDRIVE_MASK (0x1 << 6)
176 #define IOCON_DDRIVE_HIGH (0x0 << 7)
178 #define IOCON_DDRIVE_ULTRAHIGH (0x1 << 7)
180 #define IOCON_DDRIVE_MASK (0x1 << 7)
181 #define IOCON_I2CMODE_STDFAST (0x0 << 8)
182 #define IOCON_I2CMODE_PIO (0x1 << 8)
183 #define IOCON_I2CMODE_MASK (0x1 << 8)
184 #define IOCON_ILO_VAL(x) (((x) & 0xFF) << 8 )
185 #define IOCON_IHI_VAL(x) (((x) & 0xFF) << 16)
186 #define IOCON_ILO_MASK (0xFF << 8)
187 #define IOCON_IHI_MASK (0xFF << 16)
193 void Chip_IOCON_Init(NSS_IOCON_T *pIOCON);
194 
199 void Chip_IOCON_DeInit(NSS_IOCON_T *pIOCON);
200 
213 void Chip_IOCON_SetPinConfig(NSS_IOCON_T *pIOCON, IOCON_PIN_T pin, int config);
214 
224 
234 
243 
253 void Chip_IOCON_GroundAnabus(NSS_IOCON_T *pIOCON, IOCON_ANABUS_T bitvector);
254 
262 void Chip_IOCON_UngroundAnabus(NSS_IOCON_T *pIOCON, IOCON_ANABUS_T bitvector);
263 
264 #endif
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__IO uint32_t ANABUSGROUND
Definition: iocon_nss.h:90
void Chip_IOCON_SetAnabusGrounded(NSS_IOCON_T *pIOCON, IOCON_ANABUS_T bitvector)
Definition: iocon_nss.h:135
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Definition: iocon_nss.h:100
void Chip_IOCON_SetPinConfig(NSS_IOCON_T *pIOCON, IOCON_PIN_T pin, int config)
Definition: iocon_nss.h:87
Definition: iocon_nss.h:128
#define __IO
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void Chip_IOCON_GroundAnabus(NSS_IOCON_T *pIOCON, IOCON_ANABUS_T bitvector)
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int Chip_IOCON_GetPinConfig(NSS_IOCON_T *pIOCON, IOCON_PIN_T pin)
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void Chip_IOCON_UngroundAnabus(NSS_IOCON_T *pIOCON, IOCON_ANABUS_T bitvector)
IOCON_ANABUS_T
Definition: iocon_nss.h:123
IOCON_ANABUS_T Chip_IOCON_GetAnabusGrounded(NSS_IOCON_T *pIOCON)
Definition: iocon_nss.h:127
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void Chip_IOCON_DeInit(NSS_IOCON_T *pIOCON)
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IOCON_PIN_T
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