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NHS31xx SW API
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12 #ifndef __FXLS8972CF__REG_H_ 13 #define __FXLS8972CF__REG_H_ 15 #ifdef ACCEL_CHIP_FXLS8972CF 17 #define REG_INT_STATUS 0x00 18 #define REG_INT_STATUS_SRC_ASLP (1<<1) 19 #define REG_INT_STATUS_SRC_ORIENT (1<<2) 20 #define REG_INT_STATUS_SRC_SDCD_WT (1<<3) 21 #define REG_INT_STATUS_SRC_SDCD_OT (1<<4) 22 #define REG_INT_STATUS_SRC_BUF (1<<5) 24 #define REG_TEMP_OUT 0x01 25 #define REG_VECM_LSB 0x02 26 #define REG_VECM_MSB 0x03 27 #define REG_OUT_X_LSB 0x04 28 #define REG_OUT_X_MSB 0x05 29 #define REG_OUT_Y_LSB 0x06 30 #define REG_OUT_Y_MSB 0x07 31 #define REG_OUT_Z_LSB 0x08 32 #define REG_OUT_Z_MSB 0x09 33 #define REG_RESERVED_REG1 0x0A 35 #define REG_BUF_STATUS 0x0B 36 #define REG_BUF_STATUS_BUF_OVF (1<<6) 37 #define REG_BUF_STATUS_BUF_WMRK (1<<7) 39 #define REG_BUF_X_LSB 0x0C 40 #define REG_BUF_X_MSB 0x0D 41 #define REG_BUF_Y_LSB 0x0E 42 #define REG_BUF_Y_MSB 0x0F 43 #define REG_BUF_Z_LSB 0x10 44 #define REG_BUF_Z_MSB 0x11 45 #define REG_PROD_REV 0x12 46 #define REG_WHO_AM_I 0x13 48 #define REG_SYS_MODE 0x14 49 #define REG_SYS_MODE_MASK (0x3<<0) 50 #define REG_SYS_MODE_STANDBY (0x0<<0) 51 #define REG_SYS_MODE_WAKE (0x1<<0) 52 #define REG_SYS_MODE_SLEEP (0x2<<0) 54 #define REG_SENS_CONFIG1 0x15 55 #define REG_SENS_CONFIG1_ACTIVE (1<<0) 56 #define REG_SENS_CONFIG1_FSR_MASK 0x06 57 #define REG_SENS_CONFIG1_FSR_BITPOS 1 58 #define REG_SENS_CONFIG1_FSR_2G (0x0<<1) 59 #define REG_SENS_CONFIG1_FSR_4G (0x1<<1) 60 #define REG_SENS_CONFIG1_FSR_8G (0x2<<1) 61 #define REG_SENS_CONFIG1_FSR_16G (0x3<<1) 70 #define REG_SENS_CONFIG1_RST (1<<7) 72 #define REG_SENS_CONFIG2 0x16 74 #define REG_SENS_CONFIG3 0x17 76 #define REG_SENS_CONFIG3_SLEEP_ODR_1_563_HZ (0xB<<0) 77 #define REG_SENS_CONFIG3_SLEEP_ODR_3_125_HZ (0xA<<0) 78 #define REG_SENS_CONFIG3_SLEEP_ODR_6_25_HZ (0x9<<0) 79 #define REG_SENS_CONFIG3_SLEEP_ODR_12_5_HZ (0x8<<0) 80 #define REG_SENS_CONFIG3_SLEEP_ODR_25_HZ (0x7<<0) 81 #define REG_SENS_CONFIG3_SLEEP_ODR_50_HZ (0x6<<0) 82 #define REG_SENS_CONFIG3_SLEEP_ODR_100_HZ (0x5<<0) 83 #define REG_SENS_CONFIG3_SLEEP_ODR_200_HZ (0x4<<0) 84 #define REG_SENS_CONFIG3_SLEEP_ODR_400_HZ (0x3<<0) 85 #define REG_SENS_CONFIG3_WAKE_ODR_1_563_HZ (0xB<<4) 86 #define REG_SENS_CONFIG3_WAKE_ODR_3_125_HZ (0xA<<4) 87 #define REG_SENS_CONFIG3_WAKE_ODR_6_25_HZ (0x9<<4) 88 #define REG_SENS_CONFIG3_WAKE_ODR_12_5_HZ (0x8<<4) 89 #define REG_SENS_CONFIG3_WAKE_ODR_25_HZ (0x7<<4) 90 #define REG_SENS_CONFIG3_WAKE_ODR_50_HZ (0x6<<4) 91 #define REG_SENS_CONFIG3_WAKE_ODR_100_HZ (0x5<<4) 92 #define REG_SENS_CONFIG3_WAKE_ODR_200_HZ (0x4<<4) 93 #define REG_SENS_CONFIG3_WAKE_ODR_400_HZ (0x3<<4) 95 #define REG_SENS_CONFIG4 0x18 96 #define REG_SENS_CONFIG4_INT_PP_OD_OPEN_DRAIN (1<<1) 97 #define REG_SENS_CONFIG4_WAKE_ORIENT (1<<4) 98 #define REG_SENS_CONFIG4_WAKE_SDCD_OT (1<<5) 99 #define REG_SENS_CONFIG4_WAKE_SDCD_WT (1<<6) 102 #define REG_SENS_CONFIG5 0x19 103 #define REG_SENS_CONFIG5_VECM_EN (1<<4) 105 #define REG_WAKE_IDLE_LSB 0x1A 106 #define REG_WAKE_IDLE_MSB 0x1B 107 #define REG_SLEEP_IDLE_LSB 0x1C 108 #define REG_SLEEP_IDLE_MSB 0x1D 109 #define REG_ASLP_COUNT_LSB 0x1E 110 #define REG_ASLP_COUNT_MSB 0x1F 112 #define REG_INT_EN 0x20 113 #define REG_INT_EN_WAKE_OUT_EN (1<<0) 114 #define REG_INT_EN_BOOT_DIS (1<<1) 115 #define REG_INT_EN_ASLP_EN (1<<2) 116 #define REG_INT_EN_ORIENT_EN (1<<3) 117 #define REG_INT_EN_SDCD_WT_EN (1<<4) 118 #define REG_INT_EN_SDCD_OT_EN (1<<5) 119 #define REG_INT_EN_SDCD_OT_EN (1<<5) 120 #define REG_INT_EN_SDCD_BUF_EN (1<<6) 122 #define REG_INT_PIN_SEL 0x21 123 #define REG_OFF_X 0x22 124 #define REG_OFF_Y 0x23 125 #define REG_OFF_Z 0x24 126 #define REG_RESERVED_REG2 0x25 128 #define REG_BUF_CONFIG1 0x26 129 #define REG_BUF_CONFIG1_BUF_MODE_DISABLED (0x0<<5) 130 #define REG_BUF_CONFIG1_BUF_MODE_STREAM (0x1<<5) 131 #define REG_BUF_CONFIG1_BUF_MODE_STOP (0x2<<5) 132 #define REG_BUF_CONFIG1_BUF_MODE_TRIGGER (0x3<<5) 134 #define REG_BUF_CONFIG2 0x27 135 #define REG_BUF_CONFIG2_BUF_FLUSH (1<<7) 137 #define REG_ORIENT_STATUS 0x28 138 #define REG_ORIENT_STATUS_BAFRO_BACK (1<<0) 139 #define REG_ORIENT_STATUS_LAPO_MASK (0x3<<1) 140 #define REG_ORIENT_STATUS_LAPO_PORTRAIT_UP (0x0<<1) 141 #define REG_ORIENT_STATUS_LAPO_PORTRAIT_DOWN (0x1<<1) 142 #define REG_ORIENT_STATUS_LAPO_LANDSCAPE_RIGHT (0x2<<1) 143 #define REG_ORIENT_STATUS_LAPO_LANDSCAPE_LEFT (0x3<<1) 144 #define REG_ORIENT_STATUS_LO (1<<6) 145 #define REG_ORIENT_STATUS_NEW_ORIENT (1<<7) 147 #define REG_ORIENT_CONFIG 0x29 148 #define REG_ORIENT_CONFIG_ORIENT_ENABLE (1<<6) 149 #define REG_ORIENT_CONFIG_ORIENT_DBCNTM (1<<7) 151 #define REG_ORIENT_DBCOUNT 0x2A 152 #define REG_ORIENT_BF_ZCOMP 0x2B 153 #define REG_ORIENT_THS 0x2C 155 #define REG_SDCD_INT_SRC1 0x2D 156 #define REG_SDCD_INT_SRC1_Z_OT_POL (1<<0) 157 #define REG_SDCD_INT_SRC1_Z_OT_EF (1<<1) 158 #define REG_SDCD_INT_SRC1_Y_OT_POL (1<<2) 159 #define REG_SDCD_INT_SRC1_Y_OT_EF (1<<3) 160 #define REG_SDCD_INT_SRC1_X_OT_POL (1<<4) 161 #define REG_SDCD_INT_SRC1_X_OT_EF (1<<5) 162 #define REG_SDCD_INT_SRC1_OT_EA (1<<7) 164 #define REG_SDCD_INT_SRC2 0x2E 166 #define REG_SDCD_CONFIG1 0x2F 167 #define REG_SDCD_CONFIG1_Z_WT_EN (1<<0) 168 #define REG_SDCD_CONFIG1_Y_WT_EN (1<<1) 169 #define REG_SDCD_CONFIG1_X_WT_EN (1<<2) 170 #define REG_SDCD_CONFIG1_Z_OT_EN (1<<3) 171 #define REG_SDCD_CONFIG1_Y_OT_EN (1<<4) 172 #define REG_SDCD_CONFIG1_X_OT_EN (1<<5) 173 #define REG_SDCD_CONFIG1_WT_ENE (1<<6) 174 #define REG_SDCD_CONFIG1_OT_ENE (1<<7) 176 #define REG_SDCD_CONFIG2 0x30 177 #define REG_SDCD_CONFIG2_SDCD_MODE (1<<1) 178 #define REG_SDCD_CONFIG2_WT_DBCTM (1<<3) 179 #define REG_SDCD_CONFIG2_OT_DBCTM (1<<4) 180 #define REG_SDCD_CONFIG2_REF_UPDM_RELATIVE (0x2<<5) 181 #define REG_SDCD_CONFIG2_REF_UPDM_ABSOLUTE (0x3<<5) 182 #define REG_SDCD_CONFIG2_SDCD_EN (1<<7) 184 #define REG_SDCD_OT_DBCNT 0x31 185 #define REG_SDCD_WT_DBCNT 0x32 186 #define REG_SDCD_LTHS_LSB 0x33 187 #define REG_SDCD_LTHS_MSB 0x34 188 #define REG_SDCD_UTHS_LSB 0x35 189 #define REG_SDCD_UTHS_MSB 0x36 190 #define REG_SELF_TEST_CONFIG1 0x37 191 #define REG_SELF_TEST_CONFIG2 0x38