NHS31xx SW API
SW Clock Restrictions

There are different clock constraints that can make it unwieldy to know the optimal system clock frequency at any moment during an application's lifetime. All constraints have been grouped here, with references to the respective modules they originate from.

Minimum clock speeds

The table below lists what is possible, given a system clock frequency:

  • The Flash read column indicates whether it can be readily read in LPM. The word possible indicates either the LPM mode must be switched off - see Chip_Flash_SetHighPowerMode, or wait states must be used
  • The Flash erase/program column indicates whether it can read flash sectors. Note that an erase/program action always requires the LPM mode to be switched off - this is taken care of automatically in the IAP library.
  • The EEPROM write column indicates whether the EPROM can be written to. For reading there are no clock restrictions.
  • The I2C columns denote whether fast and/or normal modes are possible.
  • The SPI columns denote the maximum supported data bitrate. However, it is not possible to configure the SPI clock to operate at any desired bitrate less than that maximum, as the API functions Chip_SSP_SetBitRate and Chip_SSP_SetClockRate only allow for a coarse granulation (as do the underlying SSP registers). See the section below, SPI bitrate selection for a detailed overview to achieve bitrates as close as possible to two commonly used bitrates.

SysClock Flash read Flash
erase/program
EEPROM
write
I2C master I2C slave SPI Master SPI Slave
8 MHz possible yes yes 400 kbps 400 kbps 4000 kbps 667 kbps
4 MHz yes yes yes 400 kbps 100 kbps 2000 kbps 333 kbps
2 MHz yes yes yes 100 kbps 100 kbps 1000 kbps 166 kbps
1 MHz yes yes yes 100 kbps 100 kbps 500 kbps 83 kbps
500 kHz yes yes yes no no 250 kbps 41 kbps
250 kHz yes yes no no no 125 kbps 20 kbps
125 kHz yes yes no no no 62 kbps 10 kbps
62.5 kHz yes no no no no 31 kbps 5 kbps
Note
Warning
The HW blocks mentioned above use a reference clock that is derived from the system clock. Hence the various required minimum system clock frequencies. It also incurs that changing the system clock frequency must be done with care: changing the clock frequency while communicating over I2C or SPI can result in a SW hangup; changing it while programming the flash or eeprom can result in undetermined memory contents.

SPI bitrate selection

The nearest possible values for each system clock for 2 commonly used bitrates ( 9600bps and 19200bps ) are given below:

SysClock Bitrate near t
8MHz 9592 19231
4MHz 9615 19231
2MHz 9615 19231
1MHz 9615 19231
500kHz 9615 19231
250kHz 9615 17857
125kHz 8929 20833
62.5kHz 10417 15625

As an example: at 500kHz, to get 19200bps, the closest possible value that can be set is 19231bps.

Take care when coding the SPI bitrate selection: this is done using the API Chip_SSP_SetBitRate, which first calculates a prescale divider to attain the closest possible bitrate less than or equal to the requested one, then uses Chip_SSP_SetClockRate to configure the underlying HW. Clockrate close to but higher than what was requested are not considered. If this is nonetheless desired, the solution is to request for a higher bitrate than what is ideal.

As an example: at 500kHz, to get the bitrate closest to 19200bps, you must use the value 19232 for the argument bitrate when calling Chip_SSP_SetBitRate.