NHS31xx SW API
ssp_nss.h
1 /*
2  * Copyright 2014-2020 NXP
3  * This software is owned or controlled by NXP and may only be used strictly
4  * in accordance with the applicable license terms. By expressly accepting
5  * such terms or by downloading, installing, activating and/or otherwise using
6  * the software, you are agreeing that you have read, and that you agree to
7  * comply with and are bound by, such license terms. If you do not agree to
8  * be bound by the applicable license terms, then you may not retain, install,
9  * activate or otherwise use the software.
10  */
11 
12 #ifndef __SSP_NSS_H_
13 #define __SSP_NSS_H_
14 
119 #include <stdint.h>
120 
122 typedef struct NSS_SSP_S {
123  __IO uint32_t CR0;
124  __IO uint32_t CR1;
125  __IO uint32_t DR;
126  __I uint32_t SR;
127  __IO uint32_t CPSR;
128  __IO uint32_t IMSC;
129  __I uint32_t RIS;
130  __I uint32_t MIS;
131  __O uint32_t ICR;
132 } NSS_SSP_T;
133 
135 typedef enum SSP_INT_STATUS {
136  RESET = 0,
137  SET = !RESET
139 
141 typedef enum {
142  ERROR = 0,
144 } Status;
145 
146 #define SSP_CR0_DSS(n) ((uint32_t) ((n) & 0xF))
147 #define SSP_CR0_FRF_SPI ((uint32_t) (0 << 4))
148 #define SSP_CR0_FRF_TI ((uint32_t) (1 << 4))
149 #define SSP_CR0_FRF_MICROWIRE ((uint32_t) (2 << 4))
150 #define SSP_CR0_CPOL_LO ((uint32_t) (0))
151 #define SSP_CR0_CPOL_HI ((uint32_t) (1 << 6))
152 #define SSP_CR0_CPHA_FIRST ((uint32_t) (0))
153 #define SSP_CR0_CPHA_SECOND ((uint32_t) (1 << 7))
154 #define SSP_CR0_SCR(n) ((uint32_t) ((n & 0xFF) << 8))
155 #define SSP_CR0_BITMASK ((uint32_t) (0xFFFF))
157 #define SSP_CR1_LBM_EN ((uint32_t) (1 << 0))
158 #define SSP_CR1_SSP_EN ((uint32_t) (1 << 1))
159 #define SSP_CR1_SLAVE_EN ((uint32_t) (1 << 2))
160 #define SSP_CR1_MASTER_EN ((uint32_t) (0))
161 #define SSP_CR1_SO_DISABLE ((uint32_t) (1 << 3))
162 #define SSP_CR1_BITMASK ((uint32_t) (0x0F))
164 #define SSP_CPSR_BITMASK ((uint32_t) (0xFF))
166 #define SSP_DR_BITMASK(n) ((n) & 0xFFFF)
168 #define SSP_SR_BITMASK ((uint32_t) (0x1F))
170 #define SSP_ICR_BITMASK ((uint32_t) (0x03))
173 typedef enum SSP_STATUS {
174  SSP_STAT_TFE = ((uint32_t)(1 << 0)),
175  SSP_STAT_TNF = ((uint32_t)(1 << 1)),
176  SSP_STAT_RNE = ((uint32_t)(1 << 2)),
177  SSP_STAT_RFF = ((uint32_t)(1 << 3)),
178  SSP_STAT_BSY = ((uint32_t)(1 << 4))
179 } SSP_STATUS_T;
180 
182 typedef enum SSP_INTMASK {
183  SSP_RORIM = ((uint32_t)(1 << 0)),
184  SSP_RTIM = ((uint32_t)(1 << 1)),
185  SSP_RXIM = ((uint32_t)(1 << 2)),
186  SSP_TXIM = ((uint32_t)(1 << 3)),
187  SSP_INT_MASK_BITMASK = ((uint32_t)(0xF))
188 } SSP_INTMASK_T;
189 
191 typedef enum SSP_MASKINTSTATUS {
192  SSP_RORMIS = ((uint32_t)(1 << 0)),
193  SSP_RTMIS = ((uint32_t)(1 << 1)),
194  SSP_RXMIS = ((uint32_t)(1 << 2)),
195  SSP_TXMIS = ((uint32_t)(1 << 3)),
196  SSP_MASK_INT_STAT_BITMASK = ((uint32_t)(0xF))
198 
200 typedef enum SSP_RAWINTSTATUS {
201  SSP_RORRIS = ((uint32_t)(1 << 0)),
202  SSP_RTRIS = ((uint32_t)(1 << 1)),
203  SSP_RXRIS = ((uint32_t)(1 << 2)),
204  SSP_TXRIS = ((uint32_t)(1 << 3)),
205  SSP_RAW_INT_STAT_BITMASK = ((uint32_t)(0xF))
207 
209 typedef enum SSP_INTCLEAR {
210  SSP_RORIC = 0x0,
211  SSP_RTIC = 0x1,
214 
216 typedef enum CHIP_SSP_CLOCK_FORMAT {
218  SSP_CLOCK_CPHA0_CPOL1 = (1u << 6),
219  SSP_CLOCK_CPHA1_CPOL0 = (2u << 6),
220  SSP_CLOCK_CPHA1_CPOL1 = (3u << 6),
226 
228 typedef enum CHIP_SSP_FRAME_FORMAT {
229  SSP_FRAME_FORMAT_SPI = (0 << 4),
230  SSP_FRAME_FORMAT_TI = (1u << 4),
233 
235 typedef enum CHIP_SSP_BITS {
236  SSP_BITS_4 = (3u << 0),
237  SSP_BITS_5 = (4u << 0),
238  SSP_BITS_6 = (5u << 0),
239  SSP_BITS_7 = (6u << 0),
240  SSP_BITS_8 = (7u << 0),
241  SSP_BITS_9 = (8u << 0),
242  SSP_BITS_10 = (9u << 0),
243  SSP_BITS_11 = (10u << 0),
244  SSP_BITS_12 = (11u << 0),
245  SSP_BITS_13 = (12u << 0),
246  SSP_BITS_14 = (13u << 0),
247  SSP_BITS_15 = (14u << 0),
248  SSP_BITS_16 = (15u << 0)
250 
252 typedef enum CHIP_SSP_MODE {
253  SSP_MODE_MASTER = (0 << 2),
254  SSP_MODE_SLAVE = (1u << 2),
256 
257 /* ------------------------------------------------------------------------- */
258 
263 static inline void Chip_SSP_Enable(NSS_SSP_T *pSSP)
264 {
265  pSSP->CR1 |= SSP_CR1_SSP_EN;
266 }
267 
272 static inline void Chip_SSP_Disable(NSS_SSP_T *pSSP)
273 {
274  pSSP->CR1 &= (~SSP_CR1_SSP_EN) & SSP_CR1_BITMASK;
275 }
276 
282 static inline void Chip_SSP_EnableLoopBack(NSS_SSP_T *pSSP)
283 {
284  pSSP->CR1 |= SSP_CR1_LBM_EN;
285 }
286 
292 static inline void Chip_SSP_DisableLoopBack(NSS_SSP_T *pSSP)
293 {
294  pSSP->CR1 &= (~SSP_CR1_LBM_EN) & SSP_CR1_BITMASK;
295 }
296 
310 {
311  return (pSSP->SR & Stat) ? SET : RESET;
312 }
313 
320 static inline uint32_t Chip_SSP_GetIntStatus(NSS_SSP_T *pSSP)
321 {
322  return pSSP->MIS;
323 }
324 
338 {
339  return (pSSP->RIS & RawInt) ? SET : RESET;
340 }
341 
348 static inline uint8_t Chip_SSP_GetDataSize(NSS_SSP_T *pSSP)
349 {
350  return SSP_CR0_DSS(pSSP->CR0);
351 }
352 
362 static inline void Chip_SSP_ClearIntPending(NSS_SSP_T *pSSP, SSP_INTCLEAR_T IntClear)
363 {
364  pSSP->ICR = IntClear;
365 }
366 
372 static inline void Chip_SSP_Int_Enable(NSS_SSP_T *pSSP)
373 {
374  pSSP->IMSC |= SSP_TXIM;
375 }
376 
382 static inline void Chip_SSP_Int_Disable(NSS_SSP_T *pSSP)
383 {
384  pSSP->IMSC &= (uint32_t)(~SSP_TXIM);
385 }
386 
392 static inline uint16_t Chip_SSP_ReceiveFrame(NSS_SSP_T *pSSP)
393 {
394  return (uint16_t)(SSP_DR_BITMASK(pSSP->DR));
395 }
396 
402 static inline void Chip_SSP_SendFrame(NSS_SSP_T *pSSP, uint16_t tx_data)
403 {
404  pSSP->DR = SSP_DR_BITMASK(tx_data);
405 }
406 
414 void Chip_SSP_SetClockRate(NSS_SSP_T *pSSP, uint32_t clk_rate, uint32_t prescale);
415 
433 static inline void Chip_SSP_SetFormat(NSS_SSP_T *pSSP, uint32_t bits, uint32_t frameFormat, uint32_t clockMode)
434 {
435  pSSP->CR0 = (pSSP->CR0 & ~0xFFu) | bits | frameFormat | clockMode;
436 }
437 
446 static inline void Chip_SSP_Set_Mode(NSS_SSP_T *pSSP, uint32_t mode)
447 {
448  pSSP->CR1 = (pSSP->CR1 & ~(1u << 2)) | mode;
449 }
450 
451 /* ------------------------------------------------------------------------- */
452 
454 typedef struct {
455  void *tx_data;
456  uint32_t tx_cnt;
457  void *rx_data;
458  uint32_t rx_cnt;
459  uint32_t length;
461 
462 /* ------------------------------------------------------------------------- */
463 
469 
478 
487 
499 
509 uint32_t Chip_SSP_WriteFrames_Blocking(NSS_SSP_T *pSSP, uint8_t *buffer, uint32_t buffer_len);
510 
520 uint32_t Chip_SSP_ReadFrames_Blocking(NSS_SSP_T *pSSP, uint8_t *buffer, uint32_t buffer_len);
521 
526 void Chip_SSP_Init(NSS_SSP_T *pSSP);
527 
533 void Chip_SSP_DeInit(NSS_SSP_T *pSSP);
534 
540 void Chip_SSP_SetMaster(NSS_SSP_T *pSSP, bool master);
541 
548 void Chip_SSP_SetBitRate(NSS_SSP_T *pSSP, uint32_t bitRate);
549 
556 uint32_t Chip_SSP_GetBitRate(NSS_SSP_T *pSSP);
557 
558 #endif
static void Chip_SSP_ClearIntPending(NSS_SSP_T *pSSP, SSP_INTCLEAR_T IntClear)
Definition: ssp_nss.h:362
Definition: ssp_nss.h:192
Definition: ssp_nss.h:240
Definition: ssp_nss.h:201
Status
Definition: ssp_nss.h:141
uint32_t Chip_SSP_RWFrames_Blocking(NSS_SSP_T *pSSP, Chip_SSP_DATA_SETUP_T *xf_setup)
Definition: ssp_nss.h:246
uint32_t Chip_SSP_WriteFrames_Blocking(NSS_SSP_T *pSSP, uint8_t *buffer, uint32_t buffer_len)
Definition: ssp_nss.h:143
SSP_RAWINTSTATUS_T
Definition: ssp_nss.h:200
Definition: ssp_nss.h:184
Definition: ssp_nss.h:194
Definition: ssp_nss.h:185
__IO uint32_t CR0
Definition: ssp_nss.h:123
SSP_STATUS_T
Definition: ssp_nss.h:173
Status Chip_SSP_Int_RWFrames16Bits(NSS_SSP_T *pSSP, Chip_SSP_DATA_SETUP_T *xf_setup)
Definition: ssp_nss.h:242
__IO uint32_t DR
Definition: ssp_nss.h:125
Definition: ssp_nss.h:174
Definition: ssp_nss.h:187
static uint8_t Chip_SSP_GetDataSize(NSS_SSP_T *pSSP)
Definition: ssp_nss.h:348
CHIP_SSP_BITS_T
Definition: ssp_nss.h:235
__I uint32_t SR
Definition: ssp_nss.h:126
Definition: ssp_nss.h:211
Definition: ssp_nss.h:254
Definition: ssp_nss.h:218
Definition: ssp_nss.h:196
Definition: ssp_nss.h:183
static void Chip_SSP_Int_Disable(NSS_SSP_T *pSSP)
Definition: ssp_nss.h:382
static void Chip_SSP_SendFrame(NSS_SSP_T *pSSP, uint16_t tx_data)
Definition: ssp_nss.h:402
Definition: ssp_nss.h:203
uint32_t Chip_SSP_GetBitRate(NSS_SSP_T *pSSP)
#define __IO
Definition: core_cm0plus.h:167
Definition: ssp_nss.h:237
__IO uint32_t CR1
Definition: ssp_nss.h:124
SSP_INTMASK_T
Definition: ssp_nss.h:182
#define __I
Definition: core_cm0plus.h:164
void * rx_data
Definition: ssp_nss.h:457
#define SSP_CR1_SSP_EN
Definition: ssp_nss.h:158
Definition: ssp_nss.h:231
Definition: ssp_nss.h:205
SSP_INT_STATUS_T
Definition: ssp_nss.h:135
Definition: ssp_nss.h:137
Definition: ssp_nss.h:178
__I uint32_t RIS
Definition: ssp_nss.h:129
Definition: ssp_nss.h:222
__IO uint32_t IMSC
Definition: ssp_nss.h:128
Definition: ssp_nss.h:202
CHIP_SSP_MODE_T
Definition: ssp_nss.h:252
Definition: ssp_nss.h:142
Definition: ssp_nss.h:224
#define SSP_CR1_BITMASK
Definition: ssp_nss.h:162
Definition: ssp_nss.h:217
Definition: ssp_nss.h:238
Definition: ssp_nss.h:247
Definition: ssp_nss.h:253
__I uint32_t MIS
Definition: ssp_nss.h:130
#define SSP_DR_BITMASK(n)
Definition: ssp_nss.h:166
Status Chip_SSP_Int_RWFrames8Bits(NSS_SSP_T *pSSP, Chip_SSP_DATA_SETUP_T *xf_setup)
void Chip_SSP_SetClockRate(NSS_SSP_T *pSSP, uint32_t clk_rate, uint32_t prescale)
Definition: ssp_nss.h:177
Definition: ssp_nss.h:195
uint32_t Chip_SSP_ReadFrames_Blocking(NSS_SSP_T *pSSP, uint8_t *buffer, uint32_t buffer_len)
SSP_MASKINTSTATUS_T
Definition: ssp_nss.h:191
static uint32_t Chip_SSP_GetIntStatus(NSS_SSP_T *pSSP)
Definition: ssp_nss.h:320
Definition: ssp_nss.h:212
uint32_t rx_cnt
Definition: ssp_nss.h:458
void Chip_SSP_SetBitRate(NSS_SSP_T *pSSP, uint32_t bitRate)
static void Chip_SSP_Enable(NSS_SSP_T *pSSP)
Definition: ssp_nss.h:263
Definition: ssp_nss.h:229
Definition: ssp_nss.h:244
Definition: ssp_nss.h:241
Definition: ssp_nss.h:136
uint32_t length
Definition: ssp_nss.h:459
Definition: ssp_nss.h:220
static SSP_INT_STATUS_T Chip_SSP_GetStatus(NSS_SSP_T *pSSP, SSP_STATUS_T Stat)
Definition: ssp_nss.h:309
Definition: ssp_nss.h:230
Definition: ssp_nss.h:186
void Chip_SSP_SetMaster(NSS_SSP_T *pSSP, bool master)
#define __O
Definition: core_cm0plus.h:166
Definition: ssp_nss.h:219
Definition: ssp_nss.h:248
static void Chip_SSP_SetFormat(NSS_SSP_T *pSSP, uint32_t bits, uint32_t frameFormat, uint32_t clockMode)
Definition: ssp_nss.h:433
Definition: ssp_nss.h:236
void Chip_SSP_Int_FlushData(NSS_SSP_T *pSSP)
Definition: ssp_nss.h:193
static void Chip_SSP_Set_Mode(NSS_SSP_T *pSSP, uint32_t mode)
Definition: ssp_nss.h:446
void Chip_SSP_Init(NSS_SSP_T *pSSP)
Definition: ssp_nss.h:210
Definition: ssp_nss.h:176
Definition: ssp_nss.h:454
Definition: ssp_nss.h:122
static uint16_t Chip_SSP_ReceiveFrame(NSS_SSP_T *pSSP)
Definition: ssp_nss.h:392
void Chip_SSP_DeInit(NSS_SSP_T *pSSP)
Definition: ssp_nss.h:245
SSP_INTCLEAR_T
Definition: ssp_nss.h:209
Definition: ssp_nss.h:243
CHIP_SSP_CLOCK_MODE_T
Definition: ssp_nss.h:216
static void Chip_SSP_Int_Enable(NSS_SSP_T *pSSP)
Definition: ssp_nss.h:372
Definition: ssp_nss.h:204
Definition: ssp_nss.h:221
uint32_t tx_cnt
Definition: ssp_nss.h:456
Definition: ssp_nss.h:239
#define SSP_CR1_LBM_EN
Definition: ssp_nss.h:157
#define SSP_CR0_DSS(n)
Definition: ssp_nss.h:146
static SSP_INT_STATUS_T Chip_SSP_GetRawIntStatus(NSS_SSP_T *pSSP, SSP_RAWINTSTATUS_T RawInt)
Definition: ssp_nss.h:337
CHIP_SSP_FRAME_FORMAT_T
Definition: ssp_nss.h:228
static void Chip_SSP_DisableLoopBack(NSS_SSP_T *pSSP)
Definition: ssp_nss.h:292
__O uint32_t ICR
Definition: ssp_nss.h:131
static void Chip_SSP_EnableLoopBack(NSS_SSP_T *pSSP)
Definition: ssp_nss.h:282
static void Chip_SSP_Disable(NSS_SSP_T *pSSP)
Definition: ssp_nss.h:272
__IO uint32_t CPSR
Definition: ssp_nss.h:127
Definition: ssp_nss.h:223
Definition: ssp_nss.h:175
void * tx_data
Definition: ssp_nss.h:455