NHS31xx SW API
timer_nss.h
1 /*
2  * Copyright 2014-2016,2018,2020 NXP
3  * This software is owned or controlled by NXP and may only be used strictly
4  * in accordance with the applicable license terms. By expressly accepting
5  * such terms or by downloading, installing, activating and/or otherwise using
6  * the software, you are agreeing that you have read, and that you agree to
7  * comply with and are bound by, such license terms. If you do not agree to
8  * be bound by the applicable license terms, then you may not retain, install,
9  * activate or otherwise use the software.
10  */
11 
12 #ifndef __TIMER_NSS_H_
13 #define __TIMER_NSS_H_
14 
283 typedef struct NSS_TIMER_S {
284  __IO uint32_t IR;
286  __IO uint32_t TCR;
288  __IO uint32_t TC;
290  __IO uint32_t PR;
292  __IO uint32_t PC;
295  __IO uint32_t MCR;
297  __IO uint32_t MR[4];
299  __I uint32_t RESERVED0[5]; /* Next address is 0x03C */
300  __IO uint32_t EMR;
302  __I uint32_t RESERVED1[13]; /* 0x040 - 0x070. Next address 0x074 */
303  __IO uint32_t PWMC;
304 } NSS_TIMER_T;
305 
307 typedef enum IP_TIMER_PIN_MATCH_STATE {
313 
315 typedef enum NSS_TIMER_MATCH_OUTPUT_MODE {
319 
321 #define TIMER_IR_CLR(n) (1u << (n))
322 
324 #define TIMER_MATCH_INT(n) ((1u << (n)) & 0x0F)
325 
327 #define TIMER_ENABLE ((1u << 0))
328 
329 #define TIMER_RESET ((1u << 1))
330 
332 #define TIMER_INT_ON_MATCH(n) (1u << ((n) * 3))
333 
334 #define TIMER_RESET_ON_MATCH(n) (1u << (((n) * 3) + 1))
335 
336 #define TIMER_STOP_ON_MATCH(n) (1u << (((n) * 3) + 2))
337 
344 
351 
358 static inline bool Chip_TIMER_MatchPending(NSS_TIMER_T *pTMR, int8_t matchnum)
359 {
360  return (bool) ((pTMR->IR & TIMER_MATCH_INT(matchnum)) != 0);
361 }
362 
369 static inline void Chip_TIMER_ClearMatch(NSS_TIMER_T *pTMR, int8_t matchnum)
370 {
371  pTMR->IR = TIMER_IR_CLR(matchnum);
372 }
373 
379 static inline void Chip_TIMER_Enable(NSS_TIMER_T *pTMR)
380 {
381  pTMR->TCR |= TIMER_ENABLE;
382 }
383 
389 static inline void Chip_TIMER_Disable(NSS_TIMER_T *pTMR)
390 {
391  pTMR->TCR &= ~TIMER_ENABLE;
392 }
393 
400 static inline uint32_t Chip_TIMER_ReadCount(NSS_TIMER_T *pTMR)
401 {
402  return pTMR->TC;
403 }
404 
411 static inline uint32_t Chip_TIMER_ReadPrescale(NSS_TIMER_T *pTMR)
412 {
413  return pTMR->PC;
414 }
415 
422 static inline void Chip_TIMER_PrescaleSet(NSS_TIMER_T *pTMR, uint32_t prescale)
423 {
424  pTMR->PR = prescale;
425 }
426 
434 static inline void Chip_TIMER_SetMatch(NSS_TIMER_T *pTMR, int8_t matchnum, uint32_t matchval)
435 {
436  pTMR->MR[matchnum] = matchval;
437 }
438 
443 void Chip_TIMER_Reset(NSS_TIMER_T *pTMR);
444 
451 static inline void Chip_TIMER_MatchEnableInt(NSS_TIMER_T *pTMR, int8_t matchnum)
452 {
453  pTMR->MCR |= TIMER_INT_ON_MATCH(matchnum);
454 }
455 
461 static inline void Chip_TIMER_MatchDisableInt(NSS_TIMER_T *pTMR, int8_t matchnum)
462 {
463  pTMR->MCR &= ~TIMER_INT_ON_MATCH(matchnum);
464 }
465 
471 static inline void Chip_TIMER_ResetOnMatchEnable(NSS_TIMER_T *pTMR, int8_t matchnum)
472 {
473  pTMR->MCR |= TIMER_RESET_ON_MATCH(matchnum);
474 }
475 
481 static inline void Chip_TIMER_ResetOnMatchDisable(NSS_TIMER_T *pTMR, int8_t matchnum)
482 {
483  pTMR->MCR &= ~TIMER_RESET_ON_MATCH(matchnum);
484 }
485 
491 static inline void Chip_TIMER_StopOnMatchEnable(NSS_TIMER_T *pTMR, int8_t matchnum)
492 {
493  pTMR->MCR |= TIMER_STOP_ON_MATCH(matchnum);
494 }
495 
502 static inline void Chip_TIMER_StopOnMatchDisable(NSS_TIMER_T *pTMR, int8_t matchnum)
503 {
504  pTMR->MCR &= ~TIMER_STOP_ON_MATCH(matchnum);
505 }
506 
518 void Chip_TIMER_ExtMatchControlSet(NSS_TIMER_T *pTMR, int8_t initial_state,
519  TIMER_PIN_MATCH_STATE_T matchState, int8_t matchnum);
520 
534 
542 
543 #endif
static void Chip_TIMER_MatchEnableInt(NSS_TIMER_T *pTMR, int8_t matchnum)
Definition: timer_nss.h:451
__IO uint32_t TC
Definition: timer_nss.h:288
static void Chip_TIMER_SetMatch(NSS_TIMER_T *pTMR, int8_t matchnum, uint32_t matchval)
Definition: timer_nss.h:434
Definition: timer_nss.h:283
#define TIMER_MATCH_INT(n)
Definition: timer_nss.h:324
__IO uint32_t TCR
Definition: timer_nss.h:286
void Chip_TIMER_ExtMatchControlSet(NSS_TIMER_T *pTMR, int8_t initial_state, TIMER_PIN_MATCH_STATE_T matchState, int8_t matchnum)
__IO uint32_t IR
Definition: timer_nss.h:284
#define TIMER_ENABLE
Definition: timer_nss.h:327
static void Chip_TIMER_ResetOnMatchEnable(NSS_TIMER_T *pTMR, int8_t matchnum)
Definition: timer_nss.h:471
static bool Chip_TIMER_MatchPending(NSS_TIMER_T *pTMR, int8_t matchnum)
Definition: timer_nss.h:358
CLOCK_PERIPHERAL_T
Definition: clock_nss.h:65
__IO uint32_t PR
Definition: timer_nss.h:290
void Chip_TIMER_SetMatchOutputMode(NSS_TIMER_T *pTMR, int matchnum, NSS_TIMER_MATCH_OUTPUT_MODE_T mode)
#define TIMER_STOP_ON_MATCH(n)
Definition: timer_nss.h:336
Definition: timer_nss.h:309
static void Chip_TIMER_MatchDisableInt(NSS_TIMER_T *pTMR, int8_t matchnum)
Definition: timer_nss.h:461
#define __IO
Definition: core_cm0plus.h:167
#define __I
Definition: core_cm0plus.h:164
#define TIMER_RESET_ON_MATCH(n)
Definition: timer_nss.h:334
void Chip_TIMER_Reset(NSS_TIMER_T *pTMR)
TIMER_PIN_MATCH_STATE_T
Definition: timer_nss.h:307
static uint32_t Chip_TIMER_ReadCount(NSS_TIMER_T *pTMR)
Definition: timer_nss.h:400
static void Chip_TIMER_Enable(NSS_TIMER_T *pTMR)
Definition: timer_nss.h:379
Definition: timer_nss.h:310
static uint32_t Chip_TIMER_ReadPrescale(NSS_TIMER_T *pTMR)
Definition: timer_nss.h:411
static void Chip_TIMER_ClearMatch(NSS_TIMER_T *pTMR, int8_t matchnum)
Definition: timer_nss.h:369
__IO uint32_t MR[4]
Definition: timer_nss.h:297
__IO uint32_t EMR
Definition: timer_nss.h:300
Definition: timer_nss.h:308
NSS_TIMER_MATCH_OUTPUT_MODE_T
Definition: timer_nss.h:315
NSS_TIMER_MATCH_OUTPUT_MODE_T Chip_TIMER_GetMatchOutputMode(NSS_TIMER_T *pTMR, int matchnum)
static void Chip_TIMER_ResetOnMatchDisable(NSS_TIMER_T *pTMR, int8_t matchnum)
Definition: timer_nss.h:481
#define TIMER_IR_CLR(n)
Definition: timer_nss.h:321
static void Chip_TIMER_Disable(NSS_TIMER_T *pTMR)
Definition: timer_nss.h:389
Definition: timer_nss.h:317
#define TIMER_INT_ON_MATCH(n)
Definition: timer_nss.h:332
void Chip_TIMER_Init(NSS_TIMER_T *pTMR, CLOCK_PERIPHERAL_T clk)
static void Chip_TIMER_PrescaleSet(NSS_TIMER_T *pTMR, uint32_t prescale)
Definition: timer_nss.h:422
__IO uint32_t PWMC
Definition: timer_nss.h:303
__IO uint32_t MCR
Definition: timer_nss.h:295
void Chip_TIMER_DeInit(NSS_TIMER_T *pTMR, CLOCK_PERIPHERAL_T clk)
static void Chip_TIMER_StopOnMatchDisable(NSS_TIMER_T *pTMR, int8_t matchnum)
Definition: timer_nss.h:502
static void Chip_TIMER_StopOnMatchEnable(NSS_TIMER_T *pTMR, int8_t matchnum)
Definition: timer_nss.h:491
__IO uint32_t PC
Definition: timer_nss.h:292
Definition: timer_nss.h:316
Definition: timer_nss.h:311