NHS31xx SW API
pmu: Power Management Unit driver

Detailed Description

The Power Management Unit driver (PMU) provides the API to control all the functionalities handled by the PMU HW block. The PMU driver allows controlling the:

  1. Power modes
  2. Power switches
  3. Brown-Out detector
  4. NFC power detector
  5. Wakeup pin functionality
  6. RTC block clock source

Power Architecture:
The chip has 4 separate major power domains:
  • NFC (VNFC)
  • Always-On (VDD_ALON)
  • 1.2V Internal (VDD1V2)
  • 1.6V Internal (VDD1V6)
Power may be supplied via two possible sources:
  • External power supply pin (VDDBAT)
  • Built-in RFID rectifier (part of the VNFC power domain)
The VDD_ALON power domain is directly powered by one of these two power sources. The PMU, which is in the VDD_ALON power domain, is responsible for controlling the power for the 1V2 and 1V6 internal power domains.
Both the VDDBAT pin and the VNFC power sources are connected to the VDD_ALON power domain by means of automatic switches. The switches define which power source is providing power to the VDD_ALON power domain and, consequently, the rest of the chip. The switches are, thus, never closed simultaneously.
Even when power in the VDDBAT pin is present (when voltage is lower than 1.72V, power is not considered to be present), the respective switch will only be automatically closed when the RESETN pin is deasserted (an edge from low to high is detected) or at the time power is detected at the VNFC power domain (an edge from no power detected to power detected coming from the built-in RFID rectifier). In other words, even when power in the VDDBAT pin is present, the chip is only effectively powered up when one of these two triggers is detected. This switch can be manually set back to its initial open state using the Chip_PMU_Switch_OpenVDDBat function.
When power in the VNFC domain becomes present (when voltage is lower than 1.72V, power is not considered to be present), there are three possible scenarios:
  • No power is available in the VDDBAT pin
  • Power is also available in the VDDBAT pin, but the switch is still open
  • Power is also available in the VDDBAT pin, but the switch is already closed
In the first scenario, the VNFC switch is automatically closed and the chip will be powered via VNFC.
In the second scenario, the presence of VNFC will trigger the VDDBAT switch to close. In the presence of the two power sources, the automatic switching mechanism will give priority to VDDBAT.
In the last scenario, as the switch is already closed, the IC is already being powered by the VDDBAT pin. Hence, when VNFC becomes also present, priority will continue to be given to VDDBAT.
As described above, it is always possible to manually send back the VDDBAT switch to its initial open state using the Chip_PMU_Switch_OpenVDDBat function. This can be used to manually trigger a switchover from VDDBAT to VNFC power source. So it is possible to force the IC to be powered by VNFC, however this has to be done each time power in the VNFC domain becomes present.
Switchover from one source to the other is automatically done in both directions without glitches in the VDD_ALON power domain.
The VDD_ALON power domain is hard connected to the external bondpad ring (pins), hence, it is possible to provide power to the pins from both VDDBAT or VNFC. Note that in the latter case, the VDDBAT pin will be disconnected from the bondpad ring as it is only meant to be a power source itself.
Power Modes:
Active:
This is the default power state after Power-On-Reset. In this state, all internal power domains (1V2 and 1V6) are powered. Thus, the ARM core and memories are clocked by the system clock, and peripherals are clocked (if enabled) by the system clock or a dedicated peripheral clock.
Sleep:
The only difference from Active to Sleep is that the clocking of the ARM core is stopped and program execution is suspended until an interrupt reaches the core or a reset condition is detected. All peripherals, if in use, continue operation, the processor state and registers as well as SRAM content are retained and the logic levels of pins remain static. Use the Chip_PMU_PowerMode_EnterSleep function to enter the Sleep power mode after the wake-up interrupt sources are correctly configured.
Deep Sleep:
In this power mode, as in Sleep mode, the clocking of the ARM core is also stopped . Moreover, all analog peripherals and Flash memory are powered down. However, as the SFRO keeps running, it is possible to leave the Watchdog timer or the general-purpose timers running (if required for timer controlled wake-up). The processor state and registers as well as SRAM content are retained and the logic levels of pins remain static. Use Chip_PMU_PowerMode_EnterDeepSleep to enter the Deep Sleep power mode after the wake-up interrupt source are correctly configured and all the peripheral clocks, except the ones required, are disabled.
The chip can exit the Deep Sleep power mode and resume execution on any Start Logic or Watchdog interrupt or restart execution in Active mode on a reset condition.
Deep power down:
In this power mode, all the internal power domains (1V2 and 1V6) are switched off (SFRO is stopped). In other words, everything is powered down except the VDD_ALON power domain (PMU and RTC are still powered). This means that, besides the program execution and peripherals being stopped and the ARM core state being lost, all SRAM and register content is also lost (except registers residing in the PMU and RTC). All digital functional pins are tri-stated except for the WAKEUP (if previously configured), and RESETN pins. Use the Chip_PMU_PowerMode_EnterDeepPowerDown function to enter the Deep power down power mode after the wake-up sources are correctly configured.
The chip can exit the Deep power down power mode on a reset condition, WAKEUP pin asserted (active low), RTC wake-up counter expire event or NFC powered event (NVIC or ARM core not involved). After waking up from Deep Power Down mode, the code execution is restarted (never resumed). If the chip exits Deep power down mode due to a reset condition, all the registers from the PMU and RTC are also set to their default value, including RTC counters, PMU general purpose registers and status flags.
Using the Chip_PMU_PowerMode_GetDPDWakeupReason function it is possible to know if the chip woke up from Deep Power Down as well as the reason for the wake up.
Note that, if there is a debugging session ongoing when you enter Deep power down mode, it will terminate and cannot be started again as long as the IC is in Deep power down mode.
More important details when combining the wakeup functionality with the use of the Deep power down mode can found below: see Deep power down procedure.
Off:
In this "Off" mode, it is considered that power is present in the VDDBAT pin. In this mode everything in the IC is powered off except the HW logic that detects the triggers that cause the VDDBAT switch to close and consequently power the rest of the IC (see Power Architecture).
Use the Chip_PMU_Switch_OpenVDDBat function to enter the "Off" mode. When the "Off" mode is left (due to RESETN asserted or power present in VNFC), the IC will start-up from scratch (POR).
Regardless of the power mode ("Off" is not included), RTC and PMU register values will be kept and functionality ensured until a full system reset occurs which sets all registers to their default state. A normal exit from Deep Power Down mode does not trigger a full system reset.

Power source switches:
Each power source (VDDBAT pin and VNFC power domain) has a dedicated switch that connects it to the VDD_ALON power domain. These switches behave automatically, and give priority to the VDDBAT pin, as described above.
The state of the switches can be individually checked using the Chip_PMU_Switch_GetVNFC and the Chip_PMU_Switch_GetVDDBat functions. This automatic switching mechanism can be disabled before entering Deep power down (See Chip_PMU_PowerMode_EnterDeepPowerDown). This is typically done to keep power consumption to a minimum, however, special care must be taken when entering Deep power down with the power source switches disabled when running from an almost empty battery (VDDBat ~ 1.74V). The consequences are that if the battery drains out (VDDBat < 1.74V) during Deep power down and the automatic switching mechanism is disabled, the IC won't be able to switch to VNFC power and start execution using the energy of an NFC field only.
The proposed solution is to use the Brown Out detector feature of the IC (See Brown-Out-Detector) to find out if VDDBat is below 1.8V to decide whether or not it is safe to disable the automatic switching mechanism.

Brown-Out-Detector:
The PMU provides the possibility to monitor the power source voltage and detect whether it drops to 1.8V or below. This functionality is disabled by default and can be enabled using the Chip_PMU_SetBODEnabled function. The detection of a Brown-Out condition is combined with interrupt generation. The current state of the BOD can be checked with the Chip_PMU_GetStatus function and the interrupt generation can be enabled with Chip_PMU_Int_SetEnabledMask. If enabled, the BOD functionality will be working during all power modes, although its interrupt can only be used as a wake-up source in Sleep mode. The occurrence of a BO condition can, thus, only be known after wakeup from Sleep, Deep Sleep or Deep power down.
Note that the Chip_PMU_GetStatus function will not provide the BOD interrupt flag that retains its value after triggered, but only the current status of the BOD (if the brown out condition is not present anymore, the current status will be cleared). To get the BOD interrupt flag, use the Chip_PMU_Int_GetRawStatus function.
NFC power detector:
The PMU provides the possibility to detect, in SW, the presence of power in the VNFC power domain. This functionality is always enabled and the current status of the power in the VNFC power domain can be checked using Chip_PMU_GetStatus. The respective interrupt generation can be enabled with the Chip_PMU_Int_SetEnabledMask function.
The NFC power detector functionality will be working during all power modes, although its interrupt can only be used as a wake-up source in Sleep mode (via triggering of corresponding interrupt in the NVIC). To wake-up from Deep Sleep with an NFC field, you can use the respective start logic interrupt (see System wake-up start logic).
Note that the Chip_PMU_GetStatus function will not provide the VNFC power interrupt flag that retains its value after triggered, but only the current status of the VNFC power (if the VNFC power is not present anymore, the current status will be cleared). To get the VNFC power interrupt flag, use the Chip_PMU_Int_GetRawStatus function.
Note
It is not possible to reliably detect whether the power-off mode has been left due to power present in VNFC. As mentioned, you can get the current status using Chip_PMU_GetStatus but this will not tell you whether the VDDBAT pin got connected and the IC started up due to the presence of an NFC field: it is possible that the NFC field triggers VDDBAT pin to be connected but is already gone by the time Chip_PMU_GetStatus is called; or that the field was only present after VDDBAT pin got connected (due to a different reason) but just in time for the Chip_PMU_GetStatus call.
Wakeup Pin:
The PMU provides the possibility to wakeup from Deep power down mode when a high-to-low transition in the PIO0_0 pin is detected. By default, after a reset, this functionality is disabled, meaning it is not possible to exit the Deep power down mode via the PIO0_0 pin. To enable this functionality, the application must:
General Purpose data registers:
The PMU can hold 5 words of data in its own registers which is retained during Deep power down mode. This data will only be lost after a Power-On-Reset or an external reset (RESETN pin asserted). This data region can be accessed using Chip_PMU_SetRetainedData and Chip_PMU_GetRetainedData. This data section is available to be used by the application layer as a simple data container to store data that needs to survive a Deep power down.

Warning
Each PMU block register read and write performs at least one "wait" period that may take up to 100us to complete due to hardware synchronization within the module. All the functions in this driver make at least one such register access. Impact on performance should be carefully considered especially when calling PMU driver functions in ISRs context and high-priority threads. If a PMU block register read/write preempts another PMU block register read/write, the procedure is repeated until no preemption is detected, which leads to additional "wait" period, and thus delays.

Deep power down procedure:
Entering Deep power down mode requires register changes in both NSS_PMU_T.PCON and ARM's SCB.SCR register. The function Chip_PMU_PowerMode_EnterDeepPowerDown abstracts away the necessary register changes.
When the wakeup pin functionality is enabled - using Chip_PMU_SetWakeupPinEnabled - correct usage of the Deep power down mode requires more involvement from the application. Entering the low power mode can fail, dependent on the state of the WAKEUP pin when the call is made, and the application code must take this possibility into account.
  • In case the WAKEUP pin is high, the digital part of the PMU has no problems transitioning to the different internal states, and will arrive at the request Deep power down mode. Code will not be resumed.
  • In case the wakeup pin low, the desired state cannot be entered. Instead, the processor will go to Sleep (the Sleep Deep mode) with the IC not going to Deep Power Down (nor to Deep Sleep). The Deep power down request is not cleared however, but kept pending. The pending request is continually re-checked at the rate of the TFRO, i.e. at 32 kHz.
    When an interrupt arrives, the ARM core will clear the sleep signal. This happens independently from the sampling of the wakeup pin. There are two possible outcomes at the next re-check of the pending request:
    • Either the sleep signal has been cleared, or the wakeup pin is still low. In that case, Deep power down mode is not entered. Instead, code execution resumes.
      The function Chip_PMU_PowerMode_EnterDeepPowerDown will return. The function implementation ensures the pending Deep power down request has been cleared before it returns.
    • Otherwise, if both the sleep signal has not yet been cleared and the wakeup pin is high again, Deep power down mode is entered belatedly.
Unfortunately, this leads to an increased code complexity for the application, as it must implement a code flow that can deal with the different outcomes. Applications using both the Deep power down mode and the wakeup pin functionality should follow the below recommendations.
  • Wrap the complete code flow from reset to Deep power down in a loop (line 3). In case Chip_PMU_PowerMode_EnterDeepPowerDown (line 9) returns, this will ensure that correct code can run.
  • Inside each loop, always check whether the wakeup pin is low, and act correspondingly (lines 2, 5, 7). This will ensure that a second attempt to enter the Deep power down mode, at the end of the second section of the loop, now has a bigger chance to succeed.
  • Before calling Chip_PMU_PowerMode_EnterDeepPowerDown, start a timer which generates an interrupt after a short interval, and enable the interrupt (line 8). This will ensure that only a very short amount of time is lost in the more expensive Sleep mode (when compared to the current consumption in Deep power down).
Combining all this results in a recommended basic application framework similar to this pseudo code:
1. Board_Init();
2. store cause of wakeup in local variable
3. for(;;) {
4. initialize drivers and modules
5. perform requested tasks, per the local variable's value
6. de-initialize drivers and modules
7. reset local variable to WAKEUP
8. start a timer, enabling its interrupt, and implementing a (dummy) interrupt handler.
9. Chip_PMU_PowerMode_EnterDeepPowerDown(true or false);
10. }
Example 1 - Using Sleep mode while measuring temperature:
Executed under main context:
Executed under interrupt:
/* To be called under interrupt from TSEN_IRQHandler */
temperature = Chip_TSen_NativeToCelsius(native, 10);
/* If the temperature is 21.2C, the variable "temperature" will be equal to 212. */
}
Example 2 - Using Deep Sleep mode while counting when a pin is pulled high:
Executed under main context:
Executed under interrupt:
/* To be called under interrupt from PIO0_1_IRQHandler */
counter++;
}
Example 3 - Using Deep Power Down mode and keep track of the wake-up reasons:
Executed under main context:
uint32_t counters[4];
Chip_PMU_GetRetainedData(counters, 0, 4);
if (reason == PMU_DPD_WAKEUPREASON_NONE) {
/* POR or RESETN pin asserted - (re-)setup and (re-)initialize */
memset(counters, 0, sizeof(counters));
}
else {
ASSERT(reason < 4);
/* PMU_DPD_WAKEUPREASON_NFCPOWER: Waking up from Deep Power Down due to the presence of an NFC field */
/* PMU_DPD_WAKEUPREASON_WAKEUPPIN: Waking up from Deep Power Down due to Wakeup pin toggled low */
/* PMU_DPD_WAKEUPREASON_RTC: Waking up from Deep Power Down due to RTC down counter expired */
counters[reason]++;
}
Chip_PMU_SetRetainedData(counters, 0, 4);
Chip_Clock_System_BusyWait_ms(4000); /* Give a little time for a possible debugger to break in. */

Data Structures

struct  NSS_PMU_T
 

Enumerations

enum  PMU_DPD_WAKEUPREASON_T {
  PMU_DPD_WAKEUPREASON_RTC = 1,
  PMU_DPD_WAKEUPREASON_NFCPOWER = 2,
  PMU_DPD_WAKEUPREASON_WAKEUPPIN = 3,
  PMU_DPD_WAKEUPREASON_NONE = 0xFF
}
 
enum  PMU_RTC_CLOCKSOURCE_T {
  PMU_RTC_CLOCKSOURCE_NONE = 0,
  PMU_RTC_CLOCKSOURCE_TFRO = 1
}
 
enum  PMU_INT_T {
  PMU_INT_BROWNOUT = (1 << 0),
  PMU_INT_NFCPOWER = (1 << 1),
  PMU_INT_NONE = 0,
  PMU_INT_ALL = 0x3
}
 
enum  PMU_STATUS_T {
  PMU_STATUS_BROWNOUT = (1 << 5),
  PMU_STATUS_VDD_NFC = (1 << 7)
}
 

Functions

void Chip_PMU_PowerMode_EnterSleep (void)
 
void Chip_PMU_PowerMode_EnterDeepSleep (void)
 
void Chip_PMU_PowerMode_EnterDeepPowerDown (bool enableSwitching)
 
PMU_DPD_WAKEUPREASON_T Chip_PMU_PowerMode_GetDPDWakeupReason (void)
 
bool Chip_PMU_Switch_GetVDDBat (void)
 
bool Chip_PMU_Switch_GetVNFC (void)
 
void Chip_PMU_Switch_OpenVDDBat (void)
 
void Chip_PMU_SetBODEnabled (bool enabled)
 
bool Chip_PMU_GetBODEnabled (void)
 
void Chip_PMU_SetWakeupPinEnabled (bool enabled)
 
bool Chip_PMU_GetWakeupPinEnabled (void)
 
void Chip_PMU_SetRTCClockSource (PMU_RTC_CLOCKSOURCE_T source)
 
PMU_RTC_CLOCKSOURCE_T Chip_PMU_GetRTCClockSource (void)
 
void Chip_PMU_SetRetainedData (uint32_t *pData, int offset, int size)
 
void Chip_PMU_GetRetainedData (uint32_t *pData, int offset, int size)
 
PMU_STATUS_T Chip_PMU_GetStatus (void)
 
void Chip_PMU_Int_SetEnabledMask (PMU_INT_T mask)
 
PMU_INT_T Chip_PMU_Int_GetEnabledMask (void)
 
PMU_INT_T Chip_PMU_Int_GetRawStatus (void)
 
void Chip_PMU_Int_ClearRawStatus (PMU_INT_T flags)
 
void Chip_PMU_SetAutoPowerEnabled (bool enabled)
 
bool Chip_PMU_GetAutoPowerEnabled (void)
 

Data Structure Documentation

◆ NSS_PMU_T

struct NSS_PMU_T

NSS Power Management Unit register block structure

Data Fields
__IO uint32_t PCON

Power control Register

__IO uint32_t GPREG[5]

General purpose Registers 0..4

__I uint32_t PSTAT

Power Management Unit status register

__I uint32_t RESERVED1
__I uint32_t ACCSTAT

Access status register

__IO uint32_t LDO1V6

Analog 1.6V LDO trimming

__I uint32_t RESERVED2
__IO uint32_t TMRCLKCTRL

Timer clock control register

__IO uint32_t IMSC

Interrupt mask set and clear register

__I uint32_t RIS

Raw interrupt status register

__I uint32_t MIS

Masked interrupt status register

__O uint32_t ICR

Interrupt clear register

Enumeration Type Documentation

◆ PMU_DPD_WAKEUPREASON_T

Possible reasons for waking up from Deep power down

Enumerator
PMU_DPD_WAKEUPREASON_RTC 

RTC wakeup-downcounter expired

PMU_DPD_WAKEUPREASON_NFCPOWER 

Power detected in the VNFC domain

PMU_DPD_WAKEUPREASON_WAKEUPPIN 

WAKEUP pin negative edge detected

PMU_DPD_WAKEUPREASON_NONE 

IC hasen't woken-up from Deep power down since last POR event, RESETN pin assertion or Sleep/DeepSleep mode entry

◆ PMU_RTC_CLOCKSOURCE_T

Possible clock sources for the RTC block

Enumerator
PMU_RTC_CLOCKSOURCE_NONE 

None of the clock sources is selected for the RTC block

PMU_RTC_CLOCKSOURCE_TFRO 

Represents the TFRO as clock source for the RTC block

◆ PMU_INT_T

enum PMU_INT_T

Possible PMU interrupt flags

Enumerator
PMU_INT_BROWNOUT 

Interrupt that is triggered when a Brown-Out is detected

PMU_INT_NFCPOWER 

Interrupt that is triggered when power in the VNFC domain is detected

PMU_INT_NONE 

Disable all Interrupts

PMU_INT_ALL 

Enable all Interrupts

◆ PMU_STATUS_T

Possible status conditions of the PMU block (simultaneous bits are possible)

Enumerator
PMU_STATUS_BROWNOUT 

Indicates whether a Brown-Out condition is currently being detected

PMU_STATUS_VDD_NFC 

Indicates whether power in the VNFC domain is currently being detected

Function Documentation

◆ Chip_PMU_PowerMode_EnterSleep()

void Chip_PMU_PowerMode_EnterSleep ( void  )

Sets the chip into Sleep power mode.

Note
The program execution will be blocked inside this function for as long as the chip is in Sleep mode. After the chip exits Sleep mode and the respective ISR is executed, the execution will be resumed and this function will return.
The observer flags that indicate which power modes were entered are cleared before entering this standby mode. Refer to Power Modes section for more details on the Sleep mode.

◆ Chip_PMU_PowerMode_EnterDeepSleep()

void Chip_PMU_PowerMode_EnterDeepSleep ( void  )

Sets the chip into Deep Sleep power mode.

Note
The program execution will be blocked inside this function for as long as the chip is in Deep Sleep mode. After the chip exits Deep Sleep mode and the respective ISR is executed, the execution will be resumed and this function will return.
All peripheral clocks must be disabled beforehand except for the Timers and Watchdog, if required. The power state after wakeup of some blocks must also be configured beforehand. Please refer to SysCon driver documentation.
The observer flags that indicate which power modes were entered are cleared before entering this standby mode. Refer to Power Modes section for more details on the Deep Sleep mode.

◆ Chip_PMU_PowerMode_EnterDeepPowerDown()

void Chip_PMU_PowerMode_EnterDeepPowerDown ( bool  enableSwitching)

Attempts to put the chip into Deep power down power mode.

Warning
- There is a possibility the attempt will fail. In that case, different behaviors are possible. See Deep power down procedure for important details.
Parameters
enableSwitching: Enables/Disables the automatic switching mechanism before entering Deep power down.
Warning
- Setting enableSwitching to 'true' has impact on power consumption during Deep power down. See Power Source switches chapter.
- Once in Deep power down mode, it is no longer possible to start a debug session, hence, special care must be taken when calling Chip_PMU_PowerMode_EnterDeepPowerDown with short "break-in" time between boot and the function call. In case Debug build is used, it is possible to introduce a 500ms delay by approaching an NFC field before entering Deep power down. This functionality is embedded in the Chip_PMU_PowerMode_EnterDeepPowerDown function and allows starting a debug session in ICs that would otherwise never accept a debug connection anymore. See SW Debug Considerations for more details.

◆ Chip_PMU_PowerMode_GetDPDWakeupReason()

PMU_DPD_WAKEUPREASON_T Chip_PMU_PowerMode_GetDPDWakeupReason ( void  )

Retrieves the reason for the last wakeup from Deep power down.

Warning
Changing the power mode before calling this function will reset the register NSS_PMU_T.PCON which maintains the wakeup reason. This means the wakeup reason from Deep power down is lost
Returns
An enumeration value with the wakeup reason. This value will be PMU_DPD_WAKEUPREASON_NONE when the register NSS_PMU_T.PCON has been reset.

◆ Chip_PMU_Switch_GetVDDBat()

bool Chip_PMU_Switch_GetVDDBat ( void  )

Gets the status of the VDDBAT pin power source switch

Returns
True if the switch is closed, false otherwise.
Note
Please refer to detailed documentation section for more details on how the automatic switching mechanism works.

◆ Chip_PMU_Switch_GetVNFC()

bool Chip_PMU_Switch_GetVNFC ( void  )

Gets the status of the VNFC power source switch

Returns
True if the switch is closed, false otherwise.
Note
Please refer to detailed documentation section for more details on how the automatic switching mechanism works.

◆ Chip_PMU_Switch_OpenVDDBat()

void Chip_PMU_Switch_OpenVDDBat ( void  )

Forces the VDDBAT switch to its initial open state

Note
The VBAT switch connects the VDDBAT pin to the VDD_ALON power domain.
Postcondition
The IC will enter the "Off" state if no power is present in the VNFC power domain or switch to VNFC power otherwise. See Off mode for more details.

◆ Chip_PMU_SetBODEnabled()

void Chip_PMU_SetBODEnabled ( bool  enabled)

Enables/Disables the Brown-Out detection

Parameters
enabled: If set to true enables the BOD, otherwise it disables it

◆ Chip_PMU_GetBODEnabled()

bool Chip_PMU_GetBODEnabled ( void  )

Gets the Brown-Out detection enabled status

Returns
If true the Brown-Out detection is enabled, otherwise it is disabled

◆ Chip_PMU_SetWakeupPinEnabled()

void Chip_PMU_SetWakeupPinEnabled ( bool  enabled)

Enables/Disables the wakeup pin functionality

Parameters
enabled: If set to true enables the wakeup pin functionality, otherwise it disables it
Note
For more details on how the wakeup pin is configured, refer to the "Wakeup Pin" section

◆ Chip_PMU_GetWakeupPinEnabled()

bool Chip_PMU_GetWakeupPinEnabled ( void  )

Gets the wakeup pin functionality enabled status

Returns
If true the wakeup pin functionality is enabled, otherwise it is disabled
Note
For more details on how the wakeup pin is configured, refer to the "Wakeup Pin" section

◆ Chip_PMU_SetRTCClockSource()

void Chip_PMU_SetRTCClockSource ( PMU_RTC_CLOCKSOURCE_T  source)

Sets the RTC block clock source. As there is only one possible source, this function effectively allows you to disable all RTC functionality. Gating the clock by providing PMU_RTC_CLOCKSOURCE_NONE as value for source will disable both the up and the down counter in the RTC, i.e. will disable the calendaring functionality (it becomes impossible to keep track of absolute time) and the wake-up possibility from Deep Power Down mode after a configured number of seconds. Gating the clock for the RTC will save a modest amount of power (in the order of 20 nA).

Parameters
source: see PMU_DPD_WAKEUPREASON_T
Note
The default RTC block clock source is the TFRO: PMU_RTC_CLOCKSOURCE_TFRO.

◆ Chip_PMU_GetRTCClockSource()

PMU_RTC_CLOCKSOURCE_T Chip_PMU_GetRTCClockSource ( void  )

Gets the RTC block clock source.

Returns
The clock source of the RTC block
Note
The default RTC block clock source is the TFRO: PMU_RTC_CLOCKSOURCE_TFRO.

◆ Chip_PMU_SetRetainedData()

void Chip_PMU_SetRetainedData ( uint32_t *  pData,
int  offset,
int  size 
)

Sets the required data words into the retained data section of the PMU

Parameters
pData: A pointer to the data words to be set
offset: The offset, in number of words, to where to set the first word
size: The size, in words, of the data to set
Note
The content of the retained data section of the PMU will only be lost after a POR or an external reset (RESETN pin asserted).
The retained data section length is 5 words, thus, the function will assert that the offset + size does not exceed 5 words.

◆ Chip_PMU_GetRetainedData()

void Chip_PMU_GetRetainedData ( uint32_t *  pData,
int  offset,
int  size 
)

Gets the required data words stored in the retained data section of the PMU

Parameters
pData: A pointer to where to place the retrieved data words
offset: The offset, in number of words, to where to get the first word from
size: The size, in words, of the data to get
Note
The retained data section length is 5 words, thus, the function will assert that the offset + size does not exceed 5 words.

◆ Chip_PMU_GetStatus()

PMU_STATUS_T Chip_PMU_GetStatus ( void  )

Returns the status information from the PMU block

Returns
Status conditions currently asserted in the PMU block
Note
A bit set to 1 means that the corresponding status condition is present
This function will provide the current status bit of the PMU block (once the conditions is not present anymore, the status bit will be cleared).

◆ Chip_PMU_Int_SetEnabledMask()

void Chip_PMU_Int_SetEnabledMask ( PMU_INT_T  mask)

Enables/Disables the PMU interrupts

Parameters
mask: interrupt enabled mask to set

◆ Chip_PMU_Int_GetEnabledMask()

PMU_INT_T Chip_PMU_Int_GetEnabledMask ( void  )

Retrieves the PMU interrupt enabled mask

Returns
Interrupt enabled mask

◆ Chip_PMU_Int_GetRawStatus()

PMU_INT_T Chip_PMU_Int_GetRawStatus ( void  )

Retrieves a bitVector with the RAW PMU interrupt flags

Returns
BitVector with the PMU RAW interrupt flags
Note
A bit set to 1 means that the corresponding interrupt flag is set.

◆ Chip_PMU_Int_ClearRawStatus()

void Chip_PMU_Int_ClearRawStatus ( PMU_INT_T  flags)

Clears the required PMU interrupt flags

Parameters
flags: Bitvector indicating which interrupt flags to clear

◆ Chip_PMU_SetAutoPowerEnabled()

void Chip_PMU_SetAutoPowerEnabled ( bool  enabled)

Enables/Disables automatic power supply switching between Vbat and NFC power

Parameters
enabled: If set to true enables the automatic switch-over, if false power is taken from VBAT exclusively.

◆ Chip_PMU_GetAutoPowerEnabled()

bool Chip_PMU_GetAutoPowerEnabled ( void  )

Gets the automatic power supply switching enabled status

Returns
If true the automatic switch-over is enabled, otherwise it is fixed to VBAT power.